1 /* coherent hypertransport initialization for AMD64
3 * written by Stefan Reinauer <stepan@openbios.org>
4 * (c) 2003-2004 by SuSE Linux AG
6 * (c) 2004 Tyan Computer
7 * 2004.12 yhlu added support to create routing table dynamically.
8 * it also support 8 ways too. (8 ways ladder or 8 ways crossbar)
10 * This code is licensed under GPL.
14 * This algorithm assumes a grid configuration as follows:
17 * org. : 1x1 2x1 2x2 2x3 2x4
66 #include <device/pci_def.h>
67 #include <device/pci_ids.h>
68 #include <device/hypertransport_def.h>
70 #include "arch/romcc_io.h"
74 #define enable_bsp_routing() enable_routing(0)
76 #define NODE_HT(x) PCI_DEV(0,24+x,0)
77 #define NODE_MP(x) PCI_DEV(0,24+x,1)
78 #define NODE_MC(x) PCI_DEV(0,24+x,3)
80 #define DEFAULT 0x00010101 /* default row entry */
83 #ifndef CROSS_BAR_47_56
84 #define CROSS_BAR_47_56 0
87 #ifndef TRY_HIGH_FIRST
88 #define TRY_HIGH_FIRST 0
91 #ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
92 #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
95 #ifndef K8_HT_CHECK_PENDING_LINK
96 #if CONFIG_MAX_PHYSICAL_CPUS >= 4
97 #define K8_HT_CHECK_PENDING_LINK 1
99 #define K8_HT_CHECK_PENDING_LINK 0
103 #ifndef CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
104 #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
107 #ifndef CONFIG_ENABLE_APIC_EXT_ID
108 #define CONFIG_ENABLE_APIC_EXT_ID 0
112 static inline void print_linkn (const char *strval, uint8_t byteval)
115 #if CONFIG_USE_PRINTK_IN_CAR
116 printk_debug("%s%02x\r\n", strval, byteval);
118 print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
123 static void disable_probes(void)
125 /* disable read/write/fill probes for uniprocessor setup
126 * they don't make sense if only one cpu is available
129 /* Hypetransport Transaction Control Register
131 * [ 0: 0] Disable read byte probe
133 * 1 = Probes not issued
134 * [ 1: 1] Disable Read Doubleword probe
136 * 1 = Probes not issued
137 * [ 2: 2] Disable write byte probes
139 * 1 = Probes not issued
140 * [ 3: 3] Disable Write Doubleword Probes
142 * 1 = Probes not issued.
143 * [10:10] Disable Fill Probe
144 * 0 = Probes issued for cache fills
145 * 1 = Probes not issued for cache fills.
150 print_spew("Disabling read/write/fill probes for UP... ");
152 val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
153 val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
154 HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P |
155 HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
156 pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
158 print_spew("done.\r\n");
162 static void enable_apic_ext_id(u8 node)
164 #if CONFIG_ENABLE_APIC_EXT_ID==1
165 #warning "FIXME Is the right place to enable apic ext id here?"
169 val = pci_read_config32(NODE_HT(node), 0x68);
170 val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
171 pci_write_config32(NODE_HT(node), 0x68, val);
175 static void enable_routing(u8 node)
179 /* HT Initialization Control Register
181 * [ 0: 0] Routing Table Disable
182 * 0 = Packets are routed according to routing tables
183 * 1 = Packets are routed according to the default link field
184 * [ 1: 1] Request Disable (BSP should clear this)
185 * 0 = Request packets may be generated
186 * 1 = Request packets may not be generated.
187 * [ 3: 2] Default Link (Read-only)
191 * 11 = CPU on same node
193 * - Scratch bit cleared by a cold reset
194 * [ 5: 5] BIOS Reset Detect
195 * - Scratch bit cleared by a cold reset
196 * [ 6: 6] INIT Detect
197 * - Scratch bit cleared by a warm or cold reset not by an INIT
201 /* Enable routing table */
202 print_spew("Enabling routing table for node ");
203 print_spew_hex8(node);
205 val=pci_read_config32(NODE_HT(node), 0x6c);
206 val &= ~((1<<1)|(1<<0));
207 pci_write_config32(NODE_HT(node), 0x6c, val);
209 print_spew(" done.\r\n");
212 static void fill_row(u8 node, u8 row, u32 value)
214 pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);
217 #if CONFIG_MAX_PHYSICAL_CPUS > 1
218 static u8 link_to_register(int ldt)
221 * [ 0: 3] Request Route
222 * [0] Route to this node
223 * [1] Route to Link 0
224 * [2] Route to Link 1
225 * [3] Route to Link 2
228 if (ldt&0x08) return 0x40;
229 if (ldt&0x04) return 0x20;
230 if (ldt&0x02) return 0x00;
232 /* we should never get here */
233 print_spew("Unknown Link\n");
237 static u32 get_row(u8 node, u8 row)
239 return pci_read_config32(NODE_HT(node), 0x40+(row<<2));
242 static int link_connection(u8 src, u8 dest)
244 return get_row(src, dest) & 0x0f;
247 static void rename_temp_node(u8 node)
251 print_spew("Renaming current temporary node to ");
252 print_spew_hex8(node);
254 val=pci_read_config32(NODE_HT(7), 0x60);
255 val &= (~7); /* clear low bits. */
256 val |= node; /* new node */
257 pci_write_config32(NODE_HT(7), 0x60, val);
259 print_spew(" done.\r\n");
262 static int verify_connection(u8 dest)
264 /* See if we have a valid connection to dest */
267 /* Verify that the coherent hypertransport link is
268 * established and actually working by reading the
269 * remode node's vendor/device id
271 val = pci_read_config32(NODE_HT(dest),0);
272 if(val != 0x11001022)
278 static uint16_t read_freq_cap(device_t dev, uint8_t pos)
280 /* Handle bugs in valid hypertransport frequency reporting */
284 freq_cap = pci_read_config16(dev, pos);
285 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
287 #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
288 #if CONFIG_K8_REV_F_SUPPORT == 0
289 if (!is_cpu_pre_e0())
296 id = pci_read_config32(dev, 0);
298 /* AMD K8 Unsupported 1Ghz? */
299 if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
300 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
306 static int optimize_connection(device_t node1, uint8_t link1, device_t node2, uint8_t link2)
308 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
309 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
310 uint16_t freq_cap1, freq_cap2;
311 uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2;
312 uint8_t freq, old_freq;
314 /* Set link width and frequency */
316 /* Initially assume everything is already optimized and I don't need a reset */
319 /* Get the frequency capabilities */
320 freq_cap1 = read_freq_cap(node1, link1 + PCI_HT_CAP_HOST_FREQ_CAP);
321 freq_cap2 = read_freq_cap(node2, link2 + PCI_HT_CAP_HOST_FREQ_CAP);
323 /* Calculate the highest possible frequency */
324 freq = log2(freq_cap1 & freq_cap2);
326 /* See if I am changing the link freqency */
327 old_freq = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ);
329 needs_reset |= old_freq != freq;
330 old_freq = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ);
332 needs_reset |= old_freq != freq;
334 /* Set the Calulcated link frequency */
335 pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ, freq);
336 pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ, freq);
338 /* Get the width capabilities */
339 width_cap1 = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH);
340 width_cap2 = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH);
342 /* Calculate node1's input width */
343 ln_width1 = link_width_to_pow2[width_cap1 & 7];
344 ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
345 if (ln_width1 > ln_width2) {
346 ln_width1 = ln_width2;
348 width = pow2_to_link_width[ln_width1];
349 /* Calculate node1's output width */
350 ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
351 ln_width2 = link_width_to_pow2[width_cap2 & 7];
352 if (ln_width1 > ln_width2) {
353 ln_width1 = ln_width2;
355 width |= pow2_to_link_width[ln_width1] << 4;
357 /* See if I am changing node1's width */
358 old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1);
360 needs_reset |= old_width != width;
362 /* Set node1's widths */
363 pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1, width);
365 // * Calculate node2's width */
366 width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
368 /* See if I am changing node2's width */
369 old_width = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1);
371 needs_reset |= old_width != width;
373 /* Set node2's widths */
374 pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1, width);
379 static uint8_t get_linkn_first(uint8_t byte)
381 if(byte & 0x02) { byte = 0; }
382 else if(byte & 0x04) { byte = 1; }
383 else if(byte & 0x08) { byte = 2; }
387 static uint8_t get_linkn_last(uint8_t byte)
389 if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; }
390 if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; }
391 if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; }
395 static uint8_t get_linkn_last_count(uint8_t byte)
398 if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
399 if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
400 if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
404 static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
409 for(linkn = 0; linkn<3; linkn++) {
412 regpos = 0x98 + 0x20 * linkn;
413 reg = pci_read_config32(NODE_HT(source), regpos);
414 if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/
419 fill_row(source,row, val);
422 static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
427 val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/
429 if(((source &1)!=(dest &1))
431 && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here
432 //(6,5) (7,4) should be here
437 /*for CROSS_BAR_47_56 47, 56, should be here too
438 and for 47, 56, 57, 75, 46, 64 we need to substract another link to
441 val_s = get_row(temp, source);
442 val |= ((val_s>>16) - (1<<(linkn+1)))<<16;
445 fill_row(temp,dest, val );
449 static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) {
451 val = get_row(source, dest);
452 val -= link_connection(source, kickout)<<16;
453 fill_row(source, dest, val);
456 static void opt_broadcast_rt_group(const u8 *conn, int num) {
459 for(i=0; i<num; i+=3) {
460 opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
463 static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
465 val = get_row(source, dest);
466 val += link_connection(source, kickout)<<16;
467 fill_row(source, dest, val);
470 static void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
473 for(i=0; i<num; i+=3) {
474 opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
479 static void setup_row_direct(u8 source, u8 dest, u8 linkn){
480 setup_row_direct_x(source, source, dest, linkn);
483 static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn){
484 setup_row_direct_x(7, source, dest, linkn);
487 static void setup_temp_row(u8 source, u8 dest)
489 /* copy val from (source, dest) to (source,7) */
490 fill_row(source,7,get_row(source,dest));
493 static void clear_temp_row(u8 source)
495 fill_row(source, 7, DEFAULT);
498 static void setup_remote_node(u8 node)
500 static const uint8_t pci_reg[] = {
501 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
502 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
503 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
504 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
505 0xc4, 0xcc, 0xd4, 0xdc,
506 0xc0, 0xc8, 0xd0, 0xd8,
507 0xe0, 0xe4, 0xe8, 0xec,
511 print_spew("setup_remote_node: ");
513 /* copy the default resource map from node 0 */
514 for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
518 value = pci_read_config32(NODE_MP(0), reg);
519 pci_write_config32(NODE_MP(7), reg, value);
522 print_spew("done\r\n");
525 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
528 #if CONFIG_MAX_PHYSICAL_CPUS > 2
530 static void setup_row_indirect_x(u8 temp, u8 source, u8 dest)
532 static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 diff)
535 /*for indirect connection, we need to compute the val from val_s(source, source), and val_g(source, gateway) */
542 gateway = source + 2;
544 gateway = source - 2;
547 val_s = get_row(temp, source);
548 val = get_row(temp, gateway);
555 diff = ((source&1)!=(dest &1));
558 if(diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/
560 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
562 /* Some node have two links left
563 * don't worry we only have (2, (3 as source need to handle
566 byte = get_linkn_last_count(byte);
567 if((byte>>2)>1) { /* make sure not the corner*/
569 val_s-=link_connection(temp, source-2); /* -down*/
574 val_s-=link_connection(temp, 6); // for 7,2 via 5
575 } else if (source==6){
576 val_s-=link_connection(temp, 7); // for 6,3 via 4
579 if (source < gateway) { // for 5, 4 via 7
580 val_s-=link_connection(temp, source-2);
583 val_s-=link_connection(temp, source+2); /* -up*/
591 if(diff) { /* cross rung?*/
595 val_s = get_row(temp, source);
596 val |= ((val_s>>16) - link_connection(temp, gateway))<<16;
599 fill_row(temp, dest, val);
604 static void setup_row_indirect(u8 source, u8 dest)
606 setup_row_indirect_x(source, source, dest);
609 static void setup_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
611 setup_row_indirect_x(source, source, dest, gateway, diff);
615 static void setup_row_indirect_group(const u8 *conn, int num)
620 for(i=0; i<num; i+=2) {
621 setup_row_indirect(conn[i], conn[i+1]);
623 for(i=0; i<num; i+=4) {
624 setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
631 static void setup_remote_row_indirect(u8 source, u8 dest)
633 setup_row_indirect_x(7, source, dest);
636 static void setup_remote_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
638 setup_row_indirect_x(7, source, dest, gateway, diff);
642 static void setup_remote_row_indirect_group(const u8 *conn, int num)
647 for(i=0; i<num; i+=2) {
648 setup_remote_row_indirect(conn[i], conn[i+1]);
650 for(i=0; i<num; i+=4) {
651 setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
656 #endif /*CONFIG_MAX_PHYSICAL_CPUS > 2*/
659 static void setup_uniprocessor(void)
661 print_spew("Enabling UP settings\r\n");
662 #if CONFIG_LOGICAL_CPUS==1
663 unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
669 #if CONFIG_MAX_PHYSICAL_CPUS > 2
670 static int optimize_connection_group(const u8 *opt_conn, int num) {
673 for(i=0; i<num; i+=2) {
674 needs_reset = optimize_connection(
675 NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])),
676 NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) );
682 #if CONFIG_MAX_PHYSICAL_CPUS > 1
683 static unsigned setup_smp2(void)
690 setup_row_local(0, 0); /* it will update the broadcast RT*/
693 byte = (val>>16) & 0xfe;
694 if(byte<0x2) { /* no coherent connection so get out.*/
699 /* Setup and check a temporary connection to node 1 */
700 #if TRY_HIGH_FIRST == 1
701 byte = get_linkn_last(byte); /* Max Link to node1 */
703 byte = get_linkn_first(byte); /*Min Link to node1 --- according to AMD*/
705 print_linkn("(0,1) link=", byte);
706 setup_row_direct(0,1, byte);
707 setup_temp_row(0, 1);
709 verify_connection(7);
711 /* We found 2 nodes so far */
712 val = pci_read_config32(NODE_HT(7), 0x6c);
713 byte = (val>>2) & 0x3; /*get default link on node7 to node0*/
714 print_linkn("(1,0) link=", byte);
715 setup_row_local(7,1);
716 setup_remote_row_direct(1, 0, byte);
718 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
720 byte = (val>>16) & 0xfe;
721 byte = get_linkn_last_count(byte);
722 if((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/
724 byte = (val>>16) & 0xfe;
725 #if TRY_HIGH_FIRST == 1
726 byte = get_linkn_first(byte); /* Min link to Node1 */
728 byte = get_linkn_last(byte); /* Max link to Node1*/
730 print_linkn("\t-->(0,1) link=", byte);
731 setup_row_direct(0,1, byte);
732 setup_temp_row(0, 1);
734 verify_connection(7);
736 /* We found 2 nodes so far */
737 val = pci_read_config32(NODE_HT(7), 0x6c);
738 byte = (val>>2) & 0x3; /* get default link on node7 to node0*/
739 print_linkn("\t-->(1,0) link=", byte);
740 setup_row_local(7,1);
741 setup_remote_row_direct(1, 0, byte);
745 setup_remote_node(1); /* Setup the regs on the remote node */
746 rename_temp_node(1); /* Rename Node 7 to Node 1 */
747 enable_routing(1); /* Enable routing on Node 1 */
749 /*don't need and it is done by clear_dead_links */
755 #endif /*CONFIG_MAX_PHYSICAL_CPUS > 1 */
757 #if CONFIG_MAX_PHYSICAL_CPUS > 2
759 static unsigned setup_smp4(void)
767 /* Setup and check temporary connection from Node 0 to Node 2 */
769 byte = ((val>>16) & 0xfe) - link_connection(0,1);
770 byte = get_linkn_last_count(byte);
772 if((byte>>2)==0) { /* We should have two coherent for 4p and above*/
777 byte &= 3; /* bit [3,2] is count-1*/
778 print_linkn("(0,2) link=", byte);
779 setup_row_direct(0, 2, byte); /*(0,2) direct link done*/
781 /* We found 3 nodes so far. Now setup a temporary
782 * connection from node 0 to node 3 via node 1
784 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
785 /* here should setup_row_direct(1,3) at first, before that we should find the link in node 1 to 3*/
787 byte = ((val>>16) & 0xfe) - link_connection(1,0);
788 byte = get_linkn_first(byte);
789 print_linkn("(1,3) link=", byte);
790 setup_row_direct(1,3,byte); /* (1, 3) direct link done*/
792 /* We found 4 nodes so far. Now setup all nodes for 4p */
793 // We need to make sure 0,2 and 1,3 link is set already
795 static const u8 conn4_1[] = {
800 static const u8 conn4_1[] = {
806 setup_row_indirect_group(conn4_1, ARRAY_SIZE(conn4_1));
809 verify_connection(7);
810 val = pci_read_config32(NODE_HT(7), 0x6c);
811 byte = (val>>2) & 0x3; /* get default link on 7 to 0*/
812 print_linkn("(2,0) link=", byte);
814 setup_row_local(7,2);
815 setup_remote_row_direct(2, 0, byte); /* node 2 to node 0 direct link done */
816 setup_remote_node(2); /* Setup the regs on the remote node */
818 rename_temp_node(2); /* Rename Node 7 to Node 2 */
819 enable_routing(2); /* Enable routing on Node 2 */
823 verify_connection(7);
825 val = pci_read_config32(NODE_HT(7), 0x6c);
826 byte = (val>>2) & 0x3; /* get default link on 7 to 1*/
827 print_linkn("(3,1) link=", byte);
829 setup_row_local(7,3);
830 setup_remote_row_direct(3, 1, byte); /* node 3 to node 1 direct link done */
831 setup_remote_node(3); /* Setup the regs on the remote node */
833 /* We need to init link between 2, and 3 direct link */
835 byte = ((val>>16) & 0xfe) - link_connection(2,0);
836 byte = get_linkn_last_count(byte);
837 print_linkn("(2,3) link=", byte & 3);
839 setup_row_direct(2,3, byte & 0x3);
842 verify_connection(7); /* to 3*/
844 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
845 /* We need to find out which link is to node3 */
846 if((byte>>2)==2) { /* one to node3, one to node0, one to node4*/
848 if((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/
850 byte = ((val>>16) & 0xfe) - link_connection(2,0);
851 byte = get_linkn_first(byte);
852 print_linkn("\t-->(2,3) link=", byte);
853 setup_row_direct(2,3,byte);
855 verify_connection(7); /* to 3*/
860 val = pci_read_config32(NODE_HT(7), 0x6c);
861 byte = (val>>2) & 0x3; /* get default link on 7 to 2*/
862 print_linkn("(3,2) link=", byte);
863 setup_remote_row_direct(3,2, byte);
865 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
866 /* set link from 3 to 5 before enable it*/
868 byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
869 byte = get_linkn_last_count(byte);
870 if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
871 byte &= 3; /*bit [3,2] is count-2*/
872 print_linkn("(3,5) link=", byte);
873 setup_remote_row_direct(3, 5, byte);
877 byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
878 byte = get_linkn_last_count(byte);
880 if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
881 byte &= 3; /* bit [3,2] is count-2*/
882 print_linkn("(2,4) link=", byte);
883 setup_row_direct(2, 4, byte);
887 //Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3
889 static const u8 conn4_3[] = {
893 static const u8 conn4_3[] = {
897 setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
899 /* ready to enable RT for Node 3 */
901 enable_routing(3); /* enable routing on node 3 (temp.) */
903 // beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2
905 static const u8 conn4_2[] = {
909 static const u8 conn4_2[] = {
913 setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
916 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
917 /* it will be done by clear_dead_links */
926 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 2 */
928 #if CONFIG_MAX_PHYSICAL_CPUS > 4
930 static unsigned setup_smp6(void)
938 /* Setup and check temporary connection from Node 0 to Node 4 through 2*/
940 byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
941 byte = get_linkn_last_count(byte);
943 if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
948 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3*/
949 /* set link from 3 to 5 before enable it*/
951 byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
952 byte = get_linkn_last_count(byte);
953 if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
958 /* We found 6 nodes so far. Now setup all nodes for 6p */
959 #warning "FIXME we need to find out the correct gateway for 6p"
960 static const u8 conn6_1[] = {
978 setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1));
980 for(byte=0; byte<4; byte+=2) {
981 setup_temp_row(byte,byte+2);
983 verify_connection(7);
984 val = pci_read_config32(NODE_HT(7), 0x6c);
985 byte = (val>>2) & 0x3; /*get default link on 7 to 2*/
986 print_linkn("(4,2) link=", byte);
988 setup_row_local(7,4);
989 setup_remote_row_direct(4, 2, byte);
990 setup_remote_node(4); /* Setup the regs on the remote node */
992 /* Set indirect connection to 0, to 3 */
993 //we only need to set 4,0 here
994 static const u8 conn6_2[] = {
1002 setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2));
1004 rename_temp_node(4);
1007 setup_temp_row(0,1);
1008 for(byte=0; byte<4; byte+=2) {
1009 setup_temp_row(byte+1,byte+3);
1011 verify_connection(7);
1013 val = pci_read_config32(NODE_HT(7), 0x6c);
1014 byte = (val>>2) & 0x3; /* get default link on 7 to 3*/
1015 print_linkn("(5,3) link=", byte);
1016 setup_row_local(7,5);
1017 setup_remote_row_direct(5, 3, byte);
1018 setup_remote_node(5); /* Setup the regs on the remote node */
1020 #if !CROSS_BAR_47_56
1021 /* We need to init link between 4, and 5 direct link */
1023 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1024 byte = get_linkn_last_count(byte);
1025 print_linkn("(4,5) link=", byte & 3);
1027 setup_row_direct(4,5, byte & 0x3);
1028 setup_temp_row(0,2);
1029 setup_temp_row(2,4);
1030 setup_temp_row(4,5);
1031 verify_connection(7); /* to 5*/
1033 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1034 /* We need to find out which link is to node5 */
1036 if((byte>>2)==2) { /* one to node5, one to node2, one to node6*/
1038 if((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/
1040 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1041 byte = get_linkn_first(byte);
1042 print_linkn("\t-->(4,5) link=", byte);
1043 setup_row_direct(4,5,byte);
1044 setup_temp_row(4,5);
1045 verify_connection(7); /* to 5*/
1050 val = pci_read_config32(NODE_HT(7), 0x6c);
1051 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1052 print_linkn("(5,4) link=", byte);
1053 setup_remote_row_direct(5,4, byte);
1057 byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
1058 byte = get_linkn_last_count(byte);
1059 if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
1060 byte &= 3; /*bit [3,2] is count-2*/
1061 print_linkn("(5,7) link=", byte);
1062 setup_remote_row_direct(5, 7, byte);
1067 byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
1068 byte = get_linkn_last_count(byte);
1070 if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
1071 byte &= 3; /* bit [3,2] is count-2*/
1072 print_linkn("(4,6) link=", byte);
1073 setup_row_direct(4, 6, byte);
1078 //We need to set 5,0 here only, We need to set up 5, 7 to make 5,0
1079 /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */
1080 static const u8 conn6_3[] = {
1081 #if !CROSS_BAR_47_56
1088 setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3));
1090 /* ready to enable RT for 5 */
1091 rename_temp_node(5);
1092 enable_routing(5); /* enable routing on node 5 (temp.) */
1094 static const u8 conn6_4[] = {
1095 #if !CROSS_BAR_47_56
1114 setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4));
1117 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
1118 * It will be done by clear_dead_links
1120 for(byte=0; byte<4; byte++) {
1121 clear_temp_row(byte);
1129 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 4 */
1131 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1133 static unsigned setup_smp8(void)
1141 /* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */
1144 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1146 byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
1147 byte = get_linkn_last_count(byte); /* Max link to 6*/
1148 if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
1155 byte = get_linkn_last_count(byte); /* Max link to 6*/
1156 if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/
1160 #if TRY_HIGH_FIRST == 1
1161 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1162 byte = get_linkn_first(byte); /*Min link to 6*/
1164 byte &= 3; /* bit [3,2] is count-1 or 2*/
1166 print_linkn("(4,6) link=", byte);
1167 setup_row_direct(4, 6, byte);
1170 #if !CROSS_BAR_47_56
1171 /* Setup and check temporary connection from Node 0 to Node 7 through 1, 3, 5*/
1173 byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
1174 byte = get_linkn_last_count(byte);
1175 if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
1181 /* We found 8 nodes so far. Now setup all nodes for 8p */
1182 static const u8 conn8_1[] = {
1183 #if !CROSS_BAR_47_56
1206 setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1));
1208 for(byte=0; byte<6; byte+=2) {
1209 setup_temp_row(byte,byte+2);
1211 verify_connection(7);
1212 val = pci_read_config32(NODE_HT(7), 0x6c);
1213 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1214 print_linkn("(6,4) link=", byte);
1216 setup_row_local(7,6);
1217 setup_remote_row_direct(6, 4, byte);
1218 setup_remote_node(6); /* Setup the regs on the remote node */
1219 /* Set indirect connection to 0, to 3 */
1220 #warning "FIXME we need to find out the correct gateway for 8p"
1221 static const u8 conn8_2[] = {
1222 #if !CROSS_BAR_47_56
1229 setup_remote_row_indirect_group(conn8_2, ARRAY_SIZE(conn8_2));
1233 /* here init 5, 6 */
1234 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
1236 byte = ((val>>16) & 0xfe) - link_connection(5,3);
1237 #if TRY_HIGH_FIRST == 1
1238 byte = get_linkn_first(byte);
1240 byte = get_linkn_last(byte);
1242 print_linkn("(5,6) link=", byte);
1243 setup_row_direct(5, 6, byte);
1245 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1246 for(byte=0; byte<4; byte+=2) {
1247 setup_temp_row(byte+1,byte+3);
1249 setup_temp_row(5,6);
1251 verify_connection(7);
1253 val = get_row(7,6); // to chect it if it is node6 before renaming
1254 if( (val>>16) == 1) { // it is real node 7 so swap it
1255 /* We need to recompute link to 6 */
1257 byte = ((val>>16) & 0xfe) - link_connection(5,3);
1258 #if TRY_HIGH_FIRST == 1
1259 byte = get_linkn_first(byte);
1261 byte = get_linkn_last(byte);
1263 print_linkn("\t-->(5,6) link=", byte);
1264 setup_row_direct(5, 6, byte);
1266 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1267 for(byte=0; byte<4; byte+=2) {
1268 setup_temp_row(byte+1,byte+3);
1271 setup_temp_row(5,6);
1273 verify_connection(7);
1275 val = pci_read_config32(NODE_HT(7), 0x6c);
1276 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1277 print_linkn("(6,5) link=", byte);
1278 setup_remote_row_direct(6, 5, byte);
1279 /*Till now 56, 65 done */
1282 rename_temp_node(6);
1285 #if !CROSS_BAR_47_56
1286 setup_temp_row(0,1);
1287 for(byte=0; byte<6; byte+=2) {
1288 setup_temp_row(byte+1,byte+3);
1291 verify_connection(7);
1293 val = pci_read_config32(NODE_HT(7), 0x6c);
1294 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1295 print_linkn("(7,5) link=", byte);
1296 setup_row_local(7,7);
1297 setup_remote_row_direct(7, 5, byte);
1301 byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
1302 byte = get_linkn_first(byte);
1303 print_linkn("(4,7) link=", byte);
1304 setup_row_direct(4, 7, byte);
1306 /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
1307 for(byte=0; byte<4; byte+=2) {
1308 setup_temp_row(byte,byte+2);
1311 verify_connection(7);
1313 val = pci_read_config32(NODE_HT(7), 0x6c);
1314 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1315 print_linkn("(7,4) link=", byte);
1316 setup_row_local(7,7);
1317 setup_remote_row_direct(7, 4, byte);
1318 /* till now 4-7, 7-4 done. */
1320 setup_remote_node(7); /* Setup the regs on the remote node */
1323 /* here init 5, 7 */
1324 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
1326 byte = ((val>>16) & 0xfe) - link_connection(5,3) - link_connection(5,6);
1327 byte = get_linkn_first(byte);
1328 print_linkn("(5,7) link=", byte);
1329 setup_row_direct(5, 7, byte);
1331 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1332 for(byte=0; byte<4; byte+=2) {
1333 setup_temp_row(byte+1,byte+3);
1336 verify_connection(7);
1338 val = pci_read_config32(NODE_HT(7), 0x6c);
1339 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1340 print_linkn("(7,5) link=", byte);
1341 setup_remote_row_direct(7, 5, byte);
1342 /*Till now 57, 75 done */
1346 /* We need to init link between 6, and 7 direct link */
1348 #if !CROSS_BAR_47_56
1349 byte = ((val>>16) & 0xfe) - link_connection(6,4);
1351 byte = ((val>>16) & 0xfe) - link_connection(6,4) - link_connection(6,5);
1353 byte = get_linkn_first(byte);
1354 print_linkn("(6,7) link=", byte);
1355 setup_row_direct(6,7, byte);
1358 #if !CROSS_BAR_47_56
1359 byte = ((val>>16) & 0xfe) - link_connection(7,5);
1361 byte = ((val>>16) & 0xfe) - link_connection(7,5) - link_connection(7,4);
1363 byte = get_linkn_first(byte);
1364 print_linkn("(7,6) link=", byte);
1365 setup_row_direct(7,6, byte);
1367 /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */
1368 static const u8 conn8_3[] = {
1369 #if !CROSS_BAR_47_56
1370 0, 7, /* restore it*/
1392 6, 1, 5, 0, // or 4, 1
1394 6, 3, 5, 0, // or 4, 1
1396 7, 0, 4, 0, // or 5, 1
1398 7, 2, 4, 0, // or 5, 1
1401 0, 7, 2, 0, /* restore it*/
1406 2, 5, 4, 1, /* reset it */
1409 4, 1, 2, 1, /* reset it */
1412 5, 2, 3, 1, /* reset it */
1418 setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3));
1421 /* for 47, 56, 57, 75, 46, 64 we need to substract another link to
1423 static const u8 conn8_4[] = {
1446 6, 1, 7, // needed for via 5
1449 6, 3, 7, // needed for via 5
1451 7, 0, 6, // needed for via 4
1454 7, 2, 6, // needed for via 4
1459 opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
1461 static const u8 conn8_5[] = {
1467 opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
1472 /* ready to enable RT for Node 7 */
1473 enable_routing(7); /* enable routing on node 7 (temp.) */
1478 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 6 */
1481 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1483 static unsigned setup_smp(void)
1487 print_spew("Enabling SMP settings\r\n");
1489 nodes = setup_smp2();
1490 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1492 nodes = setup_smp4();
1495 #if CONFIG_MAX_PHYSICAL_CPUS > 4
1497 nodes = setup_smp6();
1500 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1502 nodes = setup_smp8();
1505 #if CONFIG_USE_PRINTK_IN_CAR
1506 printk_debug("%02x nodes initialized.\r\n", nodes);
1508 print_debug_hex8(nodes);
1509 print_debug(" nodes initialized.\r\n");
1515 static unsigned verify_mp_capabilities(unsigned nodes)
1517 unsigned node, mask;
1519 mask = 0x06; /* BigMPCap */
1521 for (node=0; node<nodes; node++) {
1522 mask &= pci_read_config32(NODE_MC(node), 0xe8);
1526 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1527 case 0x02: /* MPCap */
1529 print_err("Going back to DP\r\n");
1534 case 0x00: /* Non SMP */
1536 print_err("Going back to UP\r\n");
1547 static void clear_dead_routes(unsigned nodes)
1551 #if CONFIG_MAX_PHYSICAL_CPUS == 8
1552 if(nodes==8) return;/* don't touch (7,7)*/
1558 for(node = 7; node >= 0; node--) {
1559 for(row = 7; row >= last_row; row--) {
1560 fill_row(node, row, DEFAULT);
1564 /* Update the local row */
1565 for( node=0; node<nodes; node++) {
1567 for(row =0; row<nodes; row++) {
1568 val |= get_row(node, row);
1570 fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101);
1573 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
1575 #if CONFIG_LOGICAL_CPUS==1
1576 static unsigned verify_dualcore(unsigned nodes)
1578 unsigned node, totalcpus, tmp;
1581 for (node=0; node<nodes; node++) {
1582 tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ;
1583 totalcpus += (tmp + 1);
1591 static void coherent_ht_finalize(unsigned nodes)
1594 #if CONFIG_K8_REV_F_SUPPORT == 0
1597 #if CONFIG_LOGICAL_CPUS==1
1598 unsigned total_cpus;
1600 if ((!CONFIG_HAVE_OPTION_TABLE) ||
1601 read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
1602 total_cpus = verify_dualcore(nodes);
1609 /* set up cpu count and node count and enable Limit
1610 * Config Space Range for all available CPUs.
1611 * Also clear non coherent hypertransport bus range
1612 * registers on Hammer A0 revision.
1615 print_spew("coherent_ht_finalize\r\n");
1616 #if CONFIG_K8_REV_F_SUPPORT == 0
1617 rev_a0 = is_cpu_rev_a0();
1619 for (node = 0; node < nodes; node++) {
1622 dev = NODE_HT(node);
1624 /* Set the Total CPU and Node count in the system */
1625 val = pci_read_config32(dev, 0x60);
1626 val &= (~0x000F0070);
1627 #if CONFIG_LOGICAL_CPUS==1
1628 val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
1630 val |= ((nodes-1)<<16)|((nodes-1)<<4);
1632 pci_write_config32(dev, 0x60, val);
1634 /* Only respond to real cpu pci configuration cycles
1635 * and optimize the HT settings
1637 val=pci_read_config32(dev, HT_TRANSACTION_CONTROL);
1638 val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) |
1639 (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) |
1640 (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT));
1641 val |= HTTC_LIMIT_CLDT_CFG |
1642 (HTTC_BUF_REL_PRI_8 << HTTC_BUF_REL_PRI_SHIFT) |
1643 (3 << HTTC_MED_PRI_BYP_CNT_SHIFT) |
1644 (3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
1645 pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
1647 #if CONFIG_K8_REV_F_SUPPORT == 0
1649 pci_write_config32(dev, 0x94, 0);
1650 pci_write_config32(dev, 0xb4, 0);
1651 pci_write_config32(dev, 0xd4, 0);
1656 print_spew("done\r\n");
1659 static int apply_cpu_errata_fixes(unsigned nodes)
1662 int needs_reset = 0;
1663 for(node = 0; node < nodes; node++) {
1666 dev = NODE_MC(node);
1667 #if CONFIG_K8_REV_F_SUPPORT == 0
1668 if (is_cpu_pre_c0()) {
1671 * Limit the number of downstream posted requests to 1
1673 cmd = pci_read_config32(dev, 0x70);
1674 if ((cmd & (3 << 0)) != 2) {
1677 pci_write_config32(dev, 0x70, cmd );
1680 cmd = pci_read_config32(dev, 0x7c);
1681 if ((cmd & (3 << 4)) != 0) {
1684 pci_write_config32(dev, 0x7c, cmd );
1687 /* Clock Power/Timing Low */
1688 cmd = pci_read_config32(dev, 0xd4);
1689 if (cmd != 0x000D0001) {
1691 pci_write_config32(dev, 0xd4, cmd);
1692 needs_reset = 1; /* Needed? */
1696 else if (is_cpu_pre_d0()) { // d0 later don't need it
1699 * Set Clk Ramp Hystersis to 7
1700 * Clock Power/Timing Low
1702 cmd_ref = 0x04e20707; /* Registered */
1703 cmd = pci_read_config32(dev, 0xd4);
1704 if(cmd != cmd_ref) {
1705 pci_write_config32(dev, 0xd4, cmd_ref );
1706 needs_reset = 1; /* Needed? */
1714 static int optimize_link_read_pointers(unsigned nodes)
1717 int needs_reset = 0;
1718 for(node = 0; node < nodes; node++) {
1719 device_t f0_dev, f3_dev;
1720 uint32_t cmd_ref, cmd;
1722 f0_dev = NODE_HT(node);
1723 f3_dev = NODE_MC(node);
1724 cmd_ref = cmd = pci_read_config32(f3_dev, 0xdc);
1725 for(link = 0; link < 3; link++) {
1728 /* This works on an Athlon64 because unimplemented links return 0 */
1729 reg = 0x98 + (link * 0x20);
1730 link_type = pci_read_config32(f0_dev, reg);
1731 /* Only handle coherent links */
1732 if ((link_type & (LinkConnected | InitComplete|NonCoherent)) ==
1733 (LinkConnected|InitComplete))
1735 cmd &= ~(0xff << (link *8));
1736 cmd |= 0x25 << (link *8);
1739 if (cmd != cmd_ref) {
1740 pci_write_config32(f3_dev, 0xdc, cmd);
1747 static inline unsigned get_nodes(void)
1749 return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
1752 static int optimize_link_coherent_ht(void)
1754 int needs_reset = 0;
1758 nodes = get_nodes();
1760 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1762 needs_reset |= optimize_connection(
1763 NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
1764 NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
1767 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1769 /* optimize physical connections - by LYH */
1770 static const u8 opt_conn4[] = {
1775 needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
1779 #if CONFIG_MAX_PHYSICAL_CPUS > 4
1781 static const uint8_t opt_conn6[] ={
1784 #if !CROSS_BAR_47_56
1788 needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
1792 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1794 static const uint8_t opt_conn8[] ={
1803 needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
1809 needs_reset |= apply_cpu_errata_fixes(nodes);
1810 needs_reset |= optimize_link_read_pointers(nodes);
1815 #if RAMINIT_SYSINFO == 1
1816 static void setup_coherent_ht_domain(void)
1818 static int setup_coherent_ht_domain(void)
1824 enable_bsp_routing();
1826 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1827 nodes = setup_smp();
1828 nodes = verify_mp_capabilities(nodes);
1829 clear_dead_routes(nodes);
1833 setup_uniprocessor();
1835 coherent_ht_finalize(nodes);
1837 #if RAMINIT_SYSINFO == 0
1838 return optimize_link_coherent_ht();