5 #if K8_REV_F_SUPPORT == 1
9 /* Definitions of various K8 registers */
11 #define HT_TRANSACTION_CONTROL 0x68
12 #define HTTC_DIS_RD_B_P (1 << 0)
13 #define HTTC_DIS_RD_DW_P (1 << 1)
14 #define HTTC_DIS_WR_B_P (1 << 2)
15 #define HTTC_DIS_WR_DW_P (1 << 3)
16 #define HTTC_DIS_MTS (1 << 4)
17 #define HTTC_CPU1_EN (1 << 5)
18 #define HTTC_CPU_REQ_PASS_PW (1 << 6)
19 #define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
20 #define HTTC_DIS_P_MEM_C (1 << 8)
21 #define HTTC_DIS_RMT_MEM_C (1 << 9)
22 #define HTTC_DIS_FILL_P (1 << 10)
23 #define HTTC_RSP_PASS_PW (1 << 11)
24 #define HTTC_CHG_ISOC_TO_ORD (1 << 12)
25 #define HTTC_BUF_REL_PRI_SHIFT 13
26 #define HTTC_BUF_REL_PRI_MASK 3
27 #define HTTC_BUF_REL_PRI_64 0
28 #define HTTC_BUF_REL_PRI_16 1
29 #define HTTC_BUF_REL_PRI_8 2
30 #define HTTC_BUF_REL_PRI_2 3
31 #define HTTC_LIMIT_CLDT_CFG (1 << 15)
32 #define HTTC_LINT_EN (1 << 16)
33 #define HTTC_APIC_EXT_BRD_CST (1 << 17)
34 #define HTTC_APIC_EXT_ID (1 << 18)
35 #define HTTC_APIC_EXT_SPUR (1 << 19)
36 #define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
37 #define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
38 #define HTTC_DS_NP_REQ_LIMIT_MASK 3
39 #define HTTC_DS_NP_REQ_LIMIT_NONE 0
40 #define HTTC_DS_NP_REQ_LIMIT_1 1
41 #define HTTC_DS_NP_REQ_LIMIT_4 2
42 #define HTTC_DS_NP_REQ_LIMIT_8 3
43 #define HTTC_MED_PRI_BYP_CNT_SHIFT 24
44 #define HTTC_MED_PRI_BYP_CNT_MASK 3
45 #define HTTC_HI_PRI_BYP_CNT_SHIFT 26
46 #define HTTC_HI_PRI_BYP_CNT_MASK 3
50 #define PCI_IO_BASE0 0xc0
51 #define PCI_IO_BASE1 0xc8
52 #define PCI_IO_BASE2 0xd0
53 #define PCI_IO_BASE3 0xd8
54 #define PCI_IO_BASE_VGA_EN (1 << 4)
55 #define PCI_IO_BASE_NO_ISA (1 << 5)
59 #define DRAM_CSBASE 0x40
60 #define DRAM_CSMASK 0x60
61 #define DRAM_BANK_ADDR_MAP 0x80
63 #define DRAM_TIMING_LOW 0x88
64 #define DTL_TCL_SHIFT 0
65 #define DTL_TCL_MASK 0x7
69 #define DTL_TRC_SHIFT 4
70 #define DTL_TRC_MASK 0xf
71 #define DTL_TRC_BASE 7
73 #define DTL_TRC_MAX 22
74 #define DTL_TRFC_SHIFT 8
75 #define DTL_TRFC_MASK 0xf
76 #define DTL_TRFC_BASE 9
77 #define DTL_TRFC_MIN 9
78 #define DTL_TRFC_MAX 24
79 #define DTL_TRCD_SHIFT 12
80 #define DTL_TRCD_MASK 0x7
81 #define DTL_TRCD_BASE 0
82 #define DTL_TRCD_MIN 2
83 #define DTL_TRCD_MAX 6
84 #define DTL_TRRD_SHIFT 16
85 #define DTL_TRRD_MASK 0x7
86 #define DTL_TRRD_BASE 0
87 #define DTL_TRRD_MIN 2
88 #define DTL_TRRD_MAX 4
89 #define DTL_TRAS_SHIFT 20
90 #define DTL_TRAS_MASK 0xf
91 #define DTL_TRAS_BASE 0
92 #define DTL_TRAS_MIN 5
93 #define DTL_TRAS_MAX 15
94 #define DTL_TRP_SHIFT 24
95 #define DTL_TRP_MASK 0x7
96 #define DTL_TRP_BASE 0
99 #define DTL_TWR_SHIFT 28
100 #define DTL_TWR_MASK 0x1
101 #define DTL_TWR_BASE 2
102 #define DTL_TWR_MIN 2
103 #define DTL_TWR_MAX 3
105 #define DRAM_TIMING_HIGH 0x8c
106 #define DTH_TWTR_SHIFT 0
107 #define DTH_TWTR_MASK 0x1
108 #define DTH_TWTR_BASE 1
109 #define DTH_TWTR_MIN 1
110 #define DTH_TWTR_MAX 2
111 #define DTH_TRWT_SHIFT 4
112 #define DTH_TRWT_MASK 0x7
113 #define DTH_TRWT_BASE 1
114 #define DTH_TRWT_MIN 1
115 #define DTH_TRWT_MAX 6
116 #define DTH_TREF_SHIFT 8
117 #define DTH_TREF_MASK 0x1f
118 #define DTH_TREF_100MHZ_4K 0x00
119 #define DTH_TREF_133MHZ_4K 0x01
120 #define DTH_TREF_166MHZ_4K 0x02
121 #define DTH_TREF_200MHZ_4K 0x03
122 #define DTH_TREF_100MHZ_8K 0x08
123 #define DTH_TREF_133MHZ_8K 0x09
124 #define DTH_TREF_166MHZ_8K 0x0A
125 #define DTH_TREF_200MHZ_8K 0x0B
126 #define DTH_TWCL_SHIFT 20
127 #define DTH_TWCL_MASK 0x7
128 #define DTH_TWCL_BASE 1
129 #define DTH_TWCL_MIN 1
130 #define DTH_TWCL_MAX 2
132 #define DRAM_CONFIG_LOW 0x90
133 #define DCL_DLL_Disable (1<<0)
134 #define DCL_D_DRV (1<<1)
135 #define DCL_QFC_EN (1<<2)
136 #define DCL_DisDqsHys (1<<3)
137 #define DCL_Burst2Opt (1<<5)
138 #define DCL_DramInit (1<<8)
139 #define DCL_DualDIMMen (1<<9)
140 #define DCL_DramEnable (1<<10)
141 #define DCL_MemClrStatus (1<<11)
142 #define DCL_ESR (1<<12)
143 #define DCL_SRS (1<<13)
144 #define DCL_128BitEn (1<<16)
145 #define DCL_DimmEccEn (1<<17)
146 #define DCL_UnBufDimm (1<<18)
147 #define DCL_32ByteEn (1<<19)
148 #define DCL_x4DIMM_SHIFT 20
149 #define DCL_DisInRcvrs (1<<24)
150 #define DCL_BypMax_SHIFT 25
151 #define DCL_En2T (1<<28)
152 #define DCL_UpperCSMap (1<<29)
154 #define DRAM_CONFIG_HIGH 0x94
155 #define DCH_ASYNC_LAT_SHIFT 0
156 #define DCH_ASYNC_LAT_MASK 0xf
157 #define DCH_ASYNC_LAT_BASE 0
158 #define DCH_ASYNC_LAT_MIN 0
159 #define DCH_ASYNC_LAT_MAX 15
160 #define DCH_RDPREAMBLE_SHIFT 8
161 #define DCH_RDPREAMBLE_MASK 0xf
162 #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
163 #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
164 #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
165 #define DCH_IDLE_LIMIT_SHIFT 16
166 #define DCH_IDLE_LIMIT_MASK 0x7
167 #define DCH_IDLE_LIMIT_0 0
168 #define DCH_IDLE_LIMIT_4 1
169 #define DCH_IDLE_LIMIT_8 2
170 #define DCH_IDLE_LIMIT_16 3
171 #define DCH_IDLE_LIMIT_32 4
172 #define DCH_IDLE_LIMIT_64 5
173 #define DCH_IDLE_LIMIT_128 6
174 #define DCH_IDLE_LIMIT_256 7
175 #define DCH_DYN_IDLE_CTR_EN (1 << 19)
176 #define DCH_MEMCLK_SHIFT 20
177 #define DCH_MEMCLK_MASK 0x7
178 #define DCH_MEMCLK_100MHZ 0
179 #define DCH_MEMCLK_133MHZ 2
180 #define DCH_MEMCLK_166MHZ 5
181 #define DCH_MEMCLK_200MHZ 7
182 #define DCH_MEMCLK_VALID (1 << 25)
183 #define DCH_MEMCLK_EN0 (1 << 26)
184 #define DCH_MEMCLK_EN1 (1 << 27)
185 #define DCH_MEMCLK_EN2 (1 << 28)
186 #define DCH_MEMCLK_EN3 (1 << 29)
189 #define MCA_NB_CONFIG 0x44
190 #define MNC_ECC_EN (1 << 22)
191 #define MNC_CHIPKILL_EN (1 << 23)
192 #define SCRUB_CONTROL 0x58
196 #define SCRUB_160ns 3
197 #define SCRUB_320ns 4
198 #define SCRUB_640ns 5
199 #define SCRUB_1_28us 6
200 #define SCRUB_2_56us 7
201 #define SCRUB_5_12us 8
202 #define SCRUB_10_2us 9
203 #define SCRUB_20_5us 10
204 #define SCRUB_41_0us 11
205 #define SCRUB_81_9us 12
206 #define SCRUB_163_8us 13
207 #define SCRUB_327_7us 14
208 #define SCRUB_655_4us 15
209 #define SCRUB_1_31ms 16
210 #define SCRUB_2_62ms 17
211 #define SCRUB_5_24ms 18
212 #define SCRUB_10_49ms 19
213 #define SCRUB_20_97ms 20
214 #define SCRUB_42ms 21
215 #define SCRUB_84ms 22
216 #define SC_DRAM_SCRUB_RATE_SHFIT 0
217 #define SC_DRAM_SCRUB_RATE_MASK 0x1f
218 #define SC_L2_SCRUB_RATE_SHIFT 8
219 #define SC_L2_SCRUB_RATE_MASK 0x1f
220 #define SC_L1D_SCRUB_RATE_SHIFT 16
221 #define SC_L1D_SCRUB_RATE_MASK 0x1f
222 #define SCRUB_ADDR_LOW 0x5C
223 #define SCRUB_ADDR_HIGH 0x60
224 #define NORTHBRIDGE_CAP 0xE8
225 #define NBCAP_128Bit (1 << 0)
226 #define NBCAP_MP (1 << 1)
227 #define NBCAP_BIG_MP (1 << 2)
228 #define NBCAP_ECC (1 << 3)
229 #define NBCAP_CHIPKILL_ECC (1 << 4)
230 #define NBCAP_MEMCLK_SHIFT 5
231 #define NBCAP_MEMCLK_MASK 3
232 #define NBCAP_MEMCLK_100MHZ 3
233 #define NBCAP_MEMCLK_133MHZ 2
234 #define NBCAP_MEMCLK_166MHZ 1
235 #define NBCAP_MEMCLK_200MHZ 0
236 #define NBCAP_MEMCTRL (1 << 8)
239 #define LinkConnected (1 << 0)
240 #define InitComplete (1 << 1)
241 #define NonCoherent (1 << 2)
242 #define ConnectionPending (1 << 4)
247 #if RAMINIT_SYSINFO==1
248 struct link_pair_st {
256 } __attribute__((packed));
259 uint8_t ctrl_present[NODE_NUMS];
260 struct mem_controller ctrl[NODE_NUMS];
263 struct link_pair_st link_pair[16];// enough? only in_conherent
264 uint32_t link_pair_num;
269 } __attribute__((packed));