2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /*----------------------------------------------------------------------------
22 * TYPEDEFS, DEFINITIONS AND MACROS
24 *----------------------------------------------------------------------------
27 /* Single CPU system? */
28 #if (CONFIG_MAX_PHYSICAL_CPUS == 1)
29 #define HT_BUILD_NC_ONLY 1
32 /* Debugging Options */
34 //#define AMD_DEBUG_ERROR_STOP 1
36 /*----------------------------------------------------------------------------
39 *----------------------------------------------------------------------------
43 #define FILECODE 0xFF01
48 /* include the main HT source file */
52 /*----------------------------------------------------------------------------
55 *----------------------------------------------------------------------------
58 /* FIXME: Find a better place for these pre-ram functions. */
59 #define NODE_HT(x) NODE_PCI(x,0)
60 #define NODE_MP(x) NODE_PCI(x,1)
61 #define NODE_MC(x) NODE_PCI(x,3)
62 #define NODE_LC(x) NODE_PCI(x,4)
64 static u32 get_nodes(void)
69 dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0);
70 nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) ;
71 #if CONFIG_MAX_PHYSICAL_CPUS > 8
72 nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3);
81 * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
83 void AMD_CB_EventNotify (u8 evtClass, u16 event, u8 *pEventData0)
87 printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n");
88 printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
90 for (i = 0; i < *pEventData0; i++) {
91 printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
93 printk(BIOS_DEBUG, "\n");
99 * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
101 * This routine is called every time a non-coherent chain is processed.
102 * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
103 * swap list. The first part of the list controls the BUID assignment and the
104 * second part of the list provides the device to device linking. Device orientation
105 * can be detected automatically, or explicitly. See documentation for more details.
107 * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
108 * based on each device's unit count.
111 * @param[in] u8 node = The node on which this chain is located
112 * @param[in] u8 link = The link on the host for this chain
113 * @param[out] u8** list = supply a pointer to a list
114 * @param[out] BOOL result = true to use a manual list
115 * false to initialize the link automatically
117 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u16 link, u8 **List)
119 static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
120 /* If the BUID was adjusted in early_ht we need to do the manual override */
121 if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
122 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
123 if ((node == 0) && (link == 0)) { /* BSP SB link */
134 * void getAmdTopolist(u8 ***p)
136 * point to the stock topo list array
139 void getAmdTopolist(u8 ***p)
141 *p = (u8 **)amd_topo_list;
146 * void amd_ht_init(struct sys_info *sysinfo)
148 * AMD HT init coreboot wrapper
151 void amd_ht_init(struct sys_info *sysinfo)
154 AMD_HTBLOCK ht_wrapper = {
155 NULL, // u8 **topolist;
156 0, // u8 AutoBusStart;
157 32, // u8 AutoBusMax;
158 6, // u8 AutoBusIncrement;
159 NULL, // BOOL (*AMD_CB_IgnoreLink)();
160 NULL, // BOOL (*AMD_CB_OverrideBusNumbers)();
161 AMD_CB_ManualBUIDSwapList, // BOOL (*AMD_CB_ManualBUIDSwapList)();
162 NULL, // void (*AMD_CB_DeviceCapOverride)();
163 NULL, // void (*AMD_CB_Cpu2CpuPCBLimits)();
164 NULL, // void (*AMD_CB_IOPCBLimits)();
165 NULL, // BOOL (*AMD_CB_SkipRegang)();
166 NULL, // BOOL (*AMD_CB_CustomizeTrafficDistribution)();
167 NULL, // BOOL (*AMD_CB_CustomizeBuffers)();
168 NULL, // void (*AMD_CB_OverrideDevicePort)();
169 NULL, // void (*AMD_CB_OverrideCpuPort)();
170 AMD_CB_EventNotify // void (*AMD_CB_EventNotify) ();
173 printk(BIOS_DEBUG, "Enter amd_ht_init()\n");
174 amdHtInitialize(&ht_wrapper);
175 printk(BIOS_DEBUG, "Exit amd_ht_init()\n");