2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <cpu/x86/msr.h>
21 #include <console/console.h>
22 #include <northbridge/amd/amdfam10/amdfam10.h>
24 /*----------------------------------------------------------------------------
25 * TYPEDEFS, DEFINITIONS AND MACROS
27 *----------------------------------------------------------------------------
30 /* Single CPU system? */
31 #if (CONFIG_MAX_PHYSICAL_CPUS == 1)
32 #define HT_BUILD_NC_ONLY 1
35 /* Debugging Options */
37 //#define AMD_DEBUG_ERROR_STOP 1
39 /*----------------------------------------------------------------------------
42 *----------------------------------------------------------------------------
46 #define FILECODE 0xFF01
51 /* include the main HT source file */
55 /*----------------------------------------------------------------------------
58 *----------------------------------------------------------------------------
61 /* FIXME: Find a better place for these pre-ram functions. */
62 #define NODE_HT(x) NODE_PCI(x,0)
63 #define NODE_MP(x) NODE_PCI(x,1)
64 #define NODE_MC(x) NODE_PCI(x,3)
65 #define NODE_LC(x) NODE_PCI(x,4)
67 static u32 get_nodes(void)
72 dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0);
73 nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) ;
74 #if CONFIG_MAX_PHYSICAL_CPUS > 8
75 nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3);
84 * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
86 static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
90 printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n");
91 printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
93 for (i = 0; i < *pEventData0; i++) {
94 printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
96 printk(BIOS_DEBUG, "\n");
101 * void getAmdTopolist(u8 ***p)
103 * point to the stock topo list array
106 void getAmdTopolist(u8 ***p)
108 *p = (u8 **)amd_topo_list;
113 * void amd_ht_init(struct sys_info *sysinfo)
115 * AMD HT init coreboot wrapper
118 static void amd_ht_init(struct sys_info *sysinfo)
121 AMD_HTBLOCK ht_wrapper = {
122 NULL, // u8 **topolist;
123 0, // u8 AutoBusStart;
124 32, // u8 AutoBusMax;
125 6, // u8 AutoBusIncrement;
126 NULL, // BOOL (*AMD_CB_IgnoreLink)();
127 NULL, // BOOL (*AMD_CB_OverrideBusNumbers)();
128 AMD_CB_ManualBUIDSwapList, // BOOL (*AMD_CB_ManualBUIDSwapList)();
129 NULL, // void (*AMD_CB_DeviceCapOverride)();
130 NULL, // void (*AMD_CB_Cpu2CpuPCBLimits)();
131 NULL, // void (*AMD_CB_IOPCBLimits)();
132 NULL, // BOOL (*AMD_CB_SkipRegang)();
133 NULL, // BOOL (*AMD_CB_CustomizeTrafficDistribution)();
134 NULL, // BOOL (*AMD_CB_CustomizeBuffers)();
135 NULL, // void (*AMD_CB_OverrideDevicePort)();
136 NULL, // void (*AMD_CB_OverrideCpuPort)();
137 AMD_CB_EventNotify // void (*AMD_CB_EventNotify) ();
140 printk(BIOS_DEBUG, "Enter amd_ht_init()\n");
141 amdHtInitialize(&ht_wrapper);
142 printk(BIOS_DEBUG, "Exit amd_ht_init()\n");