2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 /*----------------------------------------------------------------------------
25 * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
27 *----------------------------------------------------------------------------
30 /*-----------------------------------------------------------------------------
31 * DEFINITIONS AND MACROS
33 *-----------------------------------------------------------------------------
38 #define MAX_PLATFORM_LINKS 64 /* 8x8 fully connected (28) + 4 chains with two HT devices */
40 /* These following are internal definitions */
41 #define ROUTETOSELF 0x0F
42 #define INVALID_LINK 0xCC /* Used in port list data structure to mark unused data entries.
43 Can also be used for no link found in a port list search */
45 /* definitions for working with the port list structure */
46 #define PORTLIST_TYPE_CPU 0
47 #define PORTLIST_TYPE_IO 1
50 * Hypertransport Capability definitions and macros
54 /* HT Host Capability */
55 /* bool isHTHostCapability(u32 reg) */
56 #define IS_HT_HOST_CAPABILITY(reg) \
57 ((reg & (u32)0xE00000FF) == (u32)0x20000008)
59 #define HT_HOST_CAP_SIZE 0x20
61 /* Host CapabilityRegisters */
62 #define HTHOST_LINK_CAPABILITY_REG 0x00
63 #define HTHOST_LINK_CONTROL_REG 0x04
64 #define HTHOST_FREQ_REV_REG 0x08
65 #define HT_HOST_REV_REV3 0x60
66 #define HTHOST_FEATURE_CAP_REG 0x0C
67 #define HTHOST_BUFFER_COUNT_REG 0x10
68 #define HTHOST_ISOC_REG 0x14
69 #define HTHOST_LINK_TYPE_REG 0x18
70 #define HTHOST_TYPE_COHERENT 3
71 #define HTHOST_TYPE_NONCOHERENT 7
72 #define HTHOST_TYPE_MASK 0x1F
74 /* HT Slave Capability (HT1 compat) */
75 #define IS_HT_SLAVE_CAPABILITY(reg) \
76 ((reg & (u32)0xE00000FF) == (u32)0x00000008)
77 #define HTSLAVE_LINK01_OFFSET 4
78 #define HTSLAVE_LINK_CONTROL_0_REG 4
79 #define HTSLAVE_FREQ_REV_0_REG 0xC
81 /* HT3 gen Capability */
82 #define IS_HT_GEN3_CAPABILITY(reg) \
83 ((reg & (u32)0xF80000FF) == (u32)0xD0000008)
84 #define HTGEN3_LINK01_OFFSET 0x10
85 #define HTGEN3_LINK_TRAINING_0_REG 0x10
87 /* HT3 Retry Capability */
88 #define IS_HT_RETRY_CAPABILITY(reg) \
89 ((reg & (u32)0xF80000FF) == (u32)0xC0000008)
91 #define HTRETRY_CONTROL_REG 4
93 /* Unit ID Clumping Capability */
94 #define IS_HT_UNITID_CAPABILITY(reg) \
95 ((reg & (u32)0xF80000FF) == (u32)0x90000008)
97 #define HTUNIT_SUPPORT_REG 4
98 #define HTUNIT_ENABLE_REG 8
100 /*----------------------------------------------------------------------------
101 * TYPEDEFS, STRUCTURES, ENUMS
103 *----------------------------------------------------------------------------
106 typedef struct cNorthBridge cNorthBridge;
108 /* A pair consists of a source node, a link to the destination node, the
109 * destination node, and its link back to source node. The even indices are
110 * the source nodes and links, and the odd indices are for the destination
115 /* This section is where the link is in the system and how to find it */
116 u8 Type; /* 0 = CPU, 1 = Device, all others reserved */
117 u8 Link; /* 0-1 for devices, 0-7 for CPUs */
118 u8 NodeID; /* The node, or a pointer to the devices parent node */
119 u8 HostLink, HostDepth; /* Link of parent node + depth in chain. Only used by devices */
120 SBDFO Pointer; /* A pointer to the device's slave HT capability, so we don't have to keep searching */
122 /* This section is for the final settings, which are written to hardware */
123 BOOL SelRegang; /* Only used for CPU->CPU links */
128 /* This section is for keeping track of capabilities and possible configurations */
133 u16 CompositeFrequencyCap;
139 * Our global state data structure
142 AMD_HTBLOCK *HtBlock;
144 u8 NodesDiscovered; /* One less than the number of nodes found in the system */
146 u8 sysMpCap; /* The maximum number of nodes that all processors are capable of */
148 /* Two ports for each link
149 * Note: The Port pair 2*N and 2*N+1 are connected together to form a link
150 * (e.g. 0,1 and 8,9 are ports on either end of an HT link) The lower number
151 * port (2*N) is the source port. The device that owns the source port is
152 * always the device closer to the BSP. (i.e. nearer the CPU in a
153 * non-coherent chain, or the CPU with the lower NodeID).
155 sPortDescriptor PortList[MAX_PLATFORM_LINKS*2];
157 /* The number of coherent links comming off of each node (i.e. the 'Degree' of the node) */
158 u8 sysDegree[MAX_NODES];
159 /* The systems adjency (sysMatrix[i][j] is true if Node_i has a link to Node_j) */
160 BOOL sysMatrix[MAX_NODES][MAX_NODES];
162 /* Same as above, but for the currently selected database entry */
163 u8 dbDegree[MAX_NODES];
164 BOOL dbMatrix[MAX_NODES][MAX_NODES];
166 u8 Perm[MAX_NODES]; /* The node mapping from the database to the system */
167 u8 ReversePerm[MAX_NODES]; /* The node mapping from the system to the database */
169 /* Data for non-coherent initilization */
171 u8 UsedCfgMapEntires;
173 /* 'This' pointer for northbridge */
177 #endif /* H3FFEAT_H */