2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 /* AMD Platform Types */
25 #define AMD_PTYPE_DSK 1
26 #define AMD_PTYPE_MOB 2
27 #define AMD_PTYPE_SVR 4
28 #define AMD_PTYPE_DC 8
29 #define AMD_PTYPE_MC 0x10
30 #define AMD_PTYPE_UMA 0x20
32 #define APIC_BAR 0x1b /* APIC_BAR register */
33 #define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */
35 #define PS_LIM_REG 0xC0010061 /* P-state Current Limit Register */
36 #define PS_CUR_LIM_SHFT 4 /* P-state Current Limit shift position */
38 #define PS_CTL_REG 0xC0010062 /* P-state Control Register */
39 #define PS_CMD_MASK_OFF 0xfffffff8 /* P-state Control Register CMD Mask OFF */
41 #define PS_STS_REG 0xC0010063 /* P-state Status Register */
42 #define PS_STS_MASK 0x7 /* P-state Status Mask */
44 #define PS_REG_BASE 0xC0010064 /* P-state Register base */
45 #define PS_MAX_REG 0xC0010068 /* Maximum P-State Register */
46 #define PS_MIN_REG 0xC0010064 /* Mimimum P-State Register */
48 /* P-state register offset */
49 #define PS_REG0 0 /* offset for P0 */
50 #define PS_REG1 1 /* offset for P1 */
51 #define PS_REG2 2 /* offset for P2 */
52 #define PS_REG3 3 /* offset for P3 */
53 #define PS_REG4 4 /* offset for P4 */
55 #define PS_PSDIS_MASK 0x7fffffff /* disable P-state register */
56 #define PS_EN_MASK 0x80000000 /* P-state register enable mask */
57 #define PS_NB_DID_MASK 0x400000 /* P-state Reg[NbDid] Mask */
58 #define PS_NB_VID_M_OFF 0x01ffffff /* P-state Reg[NbVid] Mask OFF */
59 #define PS_CPU_VID_M_ON 0x0fe00 /* P-state Reg[CpuVid] Mask On */
60 #define PS_NB_VID_M_ON 0x0fe000000 /* P-state Reg[NbVid] Mask On */
61 #define PS_CPU_VID_SHFT 9 /* P-state bit shift for CpuVid */
62 #define PS_NB_VID_SHFT 25 /* P-state bit shift for NbVid */
63 #define PS_BOTH_VID_OFF 0x01ff01ff /* Mask NbVid & CpuVid */
64 #define PS_CPU_NB_VID_SHFT 16 /* P-state bit shift from CpuVid to NbVid */
65 #define PS_NB_VID_SHFT 25 /* P-state NBVID shift */
66 #define PS_DIS 0x7fffffff /* disable P-state reg */
67 #define PS_EN 0x80000000 /* enable P-state reg */
68 #define PS_CURDIV_SHFT 8 /* P-state Current Divisor shift position */
69 #define PS_CPUDID_SHIFT 6 /* P-state CPU DID shift position */
71 /* for unfused parts */
72 #define PS_NB_VID_110V 0x48000000
73 #define PS_NB_VID_1175V 0x3c000000
74 /* NB VID 1.100V =0x12[PVI]=0x24[SVI] = 0100100b 7-bit code */
76 #define PS_NB_DID0 0 /* NB DID 0 */
77 #define PS_NB_DID1 0x400000 /* NB DID 1 */
78 #define PS_CPU_VID_110V 0x4800 /* CPU VID 1.100V */
79 #define PS_CPU_VID_1175V 0x3c00 /* CPU VID 1.175V */
80 #define PS_CPU_DID 0x40 /* CPU DID 1 = divisor of 2 */
81 #define PS_CPU_DID0 0 /* CPU DID 0 = divisor of 1 */
82 #define PS_CPU_FID_16G 0x00 /* CPU FID of 00 = 1.6GHz */
83 #define PS_CPU_FID_16G1 0x10 /* CPU FId of 16 COF = 16+16/2 = 16 */
84 #define PS_CPU_FID_18G 20 /* CPU FId of 20 COF = 20+16/2 = 18 */
85 #define PS_CPU_FID_19G 22 /* CPU FId of 20 COF = 22+16/2 = 19 */
86 #define PS_CPU_FID_20G 24 /* CPU FId of 20 COF = 24+16/2 = 20 */
87 #define PS_CPU_FID_22G 28 /* CPU FId of 2C COF = 28+16/2 = 22 */
88 #define PS_CPU_FID_30G 44 /* CPU FId of 2C COF = 44+16/2 = 30 */
92 #define PCI_DEV_BASE 24 /* System PCI device ID base */
93 #define LOCAL_APIC_ID_SHIFT 24 /* Local APCI ID shift bit # */
94 #define APIC_CID_SIZE_SHIFT 12 /* ApicCoreIdSize shift bit # */
95 #define FN_0 0 /* Function 0 */
96 #define FN_1 1 /* Function 1 */
97 #define FN_2 2 /* Function 2 */
98 #define FN_3 3 /* Function 3 */
99 #define FN_4 4 /* Function 4 */
100 #define FN_5 5 /* Function 5 */
101 #define FN_80000000 0x80000000 /* Function 8000_0000 */
102 #define FN_80000001 0x80000001 /* Function 8000_0001 */
103 #define FN_80000008 0x80000008 /* Function 8000_0008 */
105 #define LNK_INIT_REG 0x6C /* F0x6C link initialization control register */
106 #define WARM_RESET_BIT 0x10 /* bit 4 =1 : warm reset */
108 #define HTC_REG 0x64 /* hardware thermal control reg */
109 #define HTC_PS_LMT_MASK 0x8fffffff /* HtcPstateLimit mask off */
110 #define PS_LIMIT_POS 28 /* PstateLimit position for HTC & STC */
112 #define STC_REG 0x68 /* software thermal control reg */
113 #define STC_PS_LMT_MASK 0x8fffffff /* StcPstateLimit mask off */
115 #define CPTC0 0x0d4 /* Clock Power/Timing Control0 Register*/
116 #define CPTC0_MASK 0x000c0fff /* Reset mask for this register */
117 #define CPTC0_NBFID_MASK 0xffffffe0 /* NbFid mask off for this register */
118 #define CPTC0_NBFID_MON 0x1f /* NbFid mask on for this register */
119 #define NB_FID_EN 0x20 /* NbFidEn bit ON */
120 #define NB_CLKDID_ALL 0x80000000 /* NbClkDidApplyAll bit ON */
121 #define NB_CLKDID 0x40000000 /* NbClkDid value set by BIOS */
122 #define PW_STP_UP50 0x08000000 /* PowerStepUp 50nS(1000b) */
123 #define PW_STP_DN50 0x00800000 /* PowerStepDown 50nS (1000b)*/
124 #define PW_STP_UP100 0x03000000 /* PowerStepUp 100nS(0011b) */
125 #define PW_STP_DN100 0x00300000 /* PowerStepDown 100nS (0011b)*/
126 #define PW_STP_UP200 0x02000000 /* PowerStepUp 200nS(0010b) */
127 #define PW_STP_DN200 0x00200000 /* PowerStepDown 200nS (0010b)*/
128 #define PW_STP_UP400 0x00000000 /* PowerStepUp 400nS(0000b) */
129 #define PW_STP_DN400 0x00000000 /* PowerStepDown 400nS (0000b)*/
132 #define LNK_PLL_LOCK 0x00010000 /* LnkPllLock value set (01b) by BIOS */
136 #define PSTATE_CTL 0xC0010070 /* P-state Control Register */
137 #define NB_VID_POS 25 /* NbVid bit shift for position */
138 #define NB_VID_MASK_OFF 0x01ffffff /* NbVid bits mask off */
139 #define NB_VID_MASK_ON 0xfe000000 /* NbVid bits mask on */
140 #define CPU_VID_POS 0x9 /* CpuVid bit shift for position */
141 #define CPU_VID_MASK_OFF 0xffff01ff /* CpuVid bits mask off */
142 #define CPU_VID_MASK_ON 0x0000fe00 /* CpuVid bits mask on */
143 #define CPU_FID_DID_M_ON 0x000001ff /* CpuFid & CpuDid mask on */
144 #define CPU_FID_DID_M_OFF 0xfffffe00 /* CpuFid & CpuDid mask off */
145 #define NB_DID_VID_M_ON 0xfe400000 /* NbDid & NbVid mask on */
146 #define NB_DID_M_ON 0x00400000 /* NbDid mask on */
147 #define NB_DID_M_OFF 0xffbfffff /* NbDid mask off */
148 #define NB_DID_POS 22 /* NbDid bit shift for position */
149 #define PS_M_OFF 0xfff8ffff /* Cur Pstate mask off */
150 #define PS_1 0x00010000 /* P-state 1 */
151 #define PS_2 0x00020000 /* P-state 2 */
152 #define PS_CPU_DID_1 0x40 /* Cpu Did 1 */
157 #define PSTATE_STS 0xC0010071 /* P-state Status Register */
158 #define STARTUP_PS_MASK 0x7 /* StartupPstate Mask */
160 /* define for NB VID & CPU VID transition functions */
164 /* F3xD8 Clock Power/Timing Control 1 Register */
165 #define CPTC1 0xd8 /* Clock Power/Timing Control1 Register*/
166 #define VSRAMP_SLAM_MASK 0xffffff88 /* MaskOff [VSRampTime]&[VSSlamTime] */
167 #define VSRAMP_SLAM_VALUE 0x16 /* [VSRampTime]=001b&[VSSlamTime]=110b */
168 #define VS_RAMP_T 4 /* VSRampTime bit position */
169 #define PWR_PLN_SHIFT 28 /* PwrPlanes bit shift */
170 #define PWR_PLN_ON 0x10000000 /* PwrPlanes bit ON */
171 #define PWR_PLN_OFF 0x0efffffff /* PwrPlanes bit OFF */
175 /* Northbridge Capability Register */
176 #define NB_CAP 0xe8 /* Northbridge Cap Reg */
177 #define CMP_CAP_SHFT 12 /* CMP CAP - number of enabled cores */
179 /* F3xDC Clock Power/Timing Control 2 Register */
180 #define CPTC2 0xdc /* Clock Power/Timing Control2 Register*/
181 #define PS_MAX_VAL_POS 8 /* PstateMaxValue bit shift */
182 #define PS_MAX_VAL_MASK 0xfffff8ff /* PstateMaxValue Mask off */
184 #define PRCT_INFO 0x1fc /* Product Info Register */
185 #define UNI_NB_FID_BIT 2 /* UniNbFid bit position */
186 #define UNI_NB_VID_BIT 7 /* UniNbVid bit position */
187 #define SPLT_NB_FID_OFFSET 14 /* SpltNbFidOffset value bit position */
188 #define SPLT_NB_VID_OFFSET 17 /* SpltNbVidOffset value bit position */
189 #define NB_CV_UPDATE 0x01 /* F3x1FC[NbCofVidUpdated] bit mask */
190 #define NB_VID_UPDATE_ALL 0x02 /* F3x1FC[NbVidUpdatedAll] bit mask */
191 #define C_FID_DID_M_OFF 0xfffffe00 /* mask off Core FID & DID */
193 #define PW_CTL_MISC 0x0a0 /* Power Control Miscellaneous Register */
194 #define COF_VID_PROG_BIT 0x80000000 /* CofVidProg bit. 0= unfused part */
195 #define DUAL_VDD_BIT 0x40000000 /* DualVdd bit. */
196 #define NB_COFVID_UPDATE_BIT 0x01 /* NbCOFVIDUpdated bit */
197 #define PVI_MODE 0x100 /* PviMode bit mask */
198 #define VID_SLAM_OFF 0x0dfffffff /* set VidSlamMode OFF */
199 #define VID_SLAM_ON 0x020000000 /* set VidSlamMode ON */
200 #define PLLLOCK_OFF 0x0ffffc7ff /* PllLockTime Mask OFF */
201 #define PLLLOCK_DFT 0x00001800 /* PllLockTime default value = 011b */
202 #define PLLLOCK_DFT_L 0x00002800 /* PllLockTime long value = 101b */
204 /* P-state Specification register base in PCI sapce */
205 #define PS_SPEC_REG 0x1e0 /* PS Spec register base address */
206 #define PCI_REG_LEN 4 /* PCI register length */
207 #define NB_DID_MASK 0x10000 /* NbDid bit mask */
208 #define NB_DID_2 2 /* NbDid = 2 */
209 #define NB_DID_1 1 /* NbDid = 1 */
210 #define SPEC_PWRDIV_M_ON 0x06000000 /* PwrDiv mask on */
211 #define SPEC_PWRVAL_M_ON 0x01e00000 /* PwrValue mask on */
212 #define SPEC_PWRDIV_SHFT 25 /* PwrDiv shift */
213 #define SPEC_PWRVAL_SHFT 17 /* PwrValue shift */
215 /* F4x1F4 Northbridge P-state spec register */
216 #define NB_PS_SPEC_REG 0x1f4 /* Nb PS spec reg */
218 #define NM_PS_REG 5 /* number of P-state MSR registers */
220 /* sFidVidInit.outFlags defines */
221 #define PWR_CK_OK 0 /* System board check OK */
222 #define PWR_CK_NO_PS 1 /* All P-state registers are over
226 #define BIT_MASK_1 0x1
227 #define BIT_MASK_2 0x3
228 #define BIT_MASK_3 0x7
229 #define BIT_MASK_4 0x0f
230 #define BIT_MASK_5 0x1f
231 #define BIT_MASK_6 0x3f
232 #define BIT_MASK_7 0x7f
233 #define BIT_MASK_8 0x0ff
236 #define VID_1_100V 0x12 /* 1.100V */
237 #define VID_1_175V 0x1E /* 1.175V */
241 #define NB_FID_800M 0x00 /* 800MHz */
249 #define GH_REV_A2 0x4 /* GH Rev A2 logical ID, Upper half */