2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <cpu/x86/lapic.h>
25 #define HT_INIT_CONTROL 0x6c
26 #define HTIC_ColdR_Detect (1<<4)
27 #define HTIC_BIOSR_Detect (1<<5)
28 #define HTIC_INIT_Detect (1<<6)
30 /* mmconf is not ready */
31 /* io_ext is not ready */
32 static u32 cpu_init_detected(u8 nodeid)
37 dev = NODE_PCI(nodeid, 0);
38 htic = pci_io_read_config32(dev, HT_INIT_CONTROL);
40 return !!(htic & HTIC_INIT_Detect);
43 static u32 bios_reset_detected(void)
46 htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL);
48 return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
51 static u32 cold_reset_detected(void)
54 htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL);
56 return !(htic & HTIC_ColdR_Detect);
59 static u32 other_reset_detected(void) // other warm reset not started by BIOS
62 htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL);
64 return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect);
67 static void distinguish_cpu_resets(u8 nodeid)
71 device = NODE_PCI(nodeid, 0);
72 htic = pci_io_read_config32(device, HT_INIT_CONTROL);
73 htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
74 pci_io_write_config32(device, HT_INIT_CONTROL, htic);
77 static u32 warm_reset_detect(u8 nodeid)
81 device = NODE_PCI(nodeid, 0);
82 htic = pci_io_read_config32(device, HT_INIT_CONTROL);
83 return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
86 static void set_bios_reset(void)
94 nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1;
96 for(i = 0; i < nodes; i++) {
98 htic = pci_read_config32(dev, HT_INIT_CONTROL);
99 htic &= ~HTIC_BIOSR_Detect;
100 pci_write_config32(dev, HT_INIT_CONTROL, htic);
105 /* Look up a which bus a given node/link combination is on.
106 * return 0 when we can't find the answer.
108 static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three bit
113 // put node and link in correct bit
114 val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8) ;
116 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
118 config_map = pci_io_read_config32(PCI_DEV(CBB, CDB, 1), reg);
119 if ((config_map & 3) != 3) {
122 if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8) )
125 return (config_map >> 16) & 0xff;
129 #if EXT_CONF_SUPPORT == 1
130 // let's check that in extend space
131 // use the nodeid extend space to find out the bus for the linkn
138 cfg_map_dest = (1<<7)|(1<<6)|link;
140 // three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
141 dev = NODE_PCI(node, 1);
142 for(j=0; j<64; j++) {
143 pci_io_write_config32(dev, 0x110, j | (6<<28));
144 tempreg = pci_io_read_config32(dev, 0x114);
145 for(i=0; i<=3; i++) {
147 if((tempreg & ((1<<7)|(1<<6)|0x3f)) == cfg_map_dest) {
148 return (i+(j<<2)); //busn_min
157 static u32 get_sblk(void)
160 /* read PCI_DEV(CBB,CDB,0) 0x64 bit [8:9] to find out SbLink m */
161 reg = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), 0x64);
162 return ((reg>>8) & 3) ;
166 static u8 get_sbbusn(u8 sblk)
168 return node_link_to_bus(0, sblk);