2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/hypertransport.h>
32 #include <cpu/x86/lapic.h>
34 #if CONFIG_LOGICAL_CPUS==1
35 #include <cpu/amd/multicore.h>
36 #include <pc80/mc146818rtc.h>
40 #include "root_complex/chip.h"
41 #include "northbridge.h"
45 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
46 #include <cpu/amd/model_10xxx_rev.h>
49 #include <cpu/amd/amdfam10_sysconf.h>
51 struct amdfam10_sysconf_t sysconf;
53 #define FX_DEVS NODE_NUMS
54 static device_t __f0_dev[FX_DEVS];
55 static device_t __f1_dev[FX_DEVS];
56 static device_t __f2_dev[FX_DEVS];
57 static device_t __f4_dev[FX_DEVS];
58 static unsigned fx_devs=0;
60 device_t get_node_pci(u32 nodeid, u32 fn)
64 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
66 return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
70 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
74 static void get_fx_devs(void)
77 for(i = 0; i < FX_DEVS; i++) {
78 __f0_dev[i] = get_node_pci(i, 0);
79 __f1_dev[i] = get_node_pci(i, 1);
80 __f2_dev[i] = get_node_pci(i, 2);
81 __f4_dev[i] = get_node_pci(i, 4);
82 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
85 if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
86 die("Cannot find 0:0x18.[0|1]\n");
90 static u32 f1_read_config32(unsigned reg)
94 return pci_read_config32(__f1_dev[0], reg);
97 static void f1_write_config32(unsigned reg, u32 value)
102 for(i = 0; i < fx_devs; i++) {
105 if (dev && dev->enabled) {
106 pci_write_config32(dev, reg, value);
111 static u32 amdfam10_nodeid(device_t dev)
115 busn = dev->bus->secondary;
116 if(busn != CONFIG_CBB) {
117 return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
119 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
123 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
127 #include "amdfam10_conf.c"
129 static void set_vga_enable_reg(u32 nodeid, u32 linkn)
133 val = 1 | (nodeid<<4) | (linkn<<12);
134 /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,
136 f1_write_config32(0xf4, val);
140 static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink,
141 u32 max, u32 offset_unitid)
143 // I want to put sb chain in bus 0 can I?
149 u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
152 u32 is_sublink1 = (link_num>3);
156 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
161 #if CONFIG_HT3_SUPPORT==1
165 regpos = 0x170 + 4 * (link_num&3); // it is only on sublink0
166 reg = pci_read_config32(dev, regpos);
167 if(reg & 1) return max; // already ganged no sblink1
168 devx = get_node_pci(nodeid, 4);
174 link->cap = 0x80 + ((link_num&3) *0x20);
176 link_type = pci_read_config32(devx, link->cap + 0x18);
177 } while(link_type & ConnectionPending);
178 if (!(link_type & LinkConnected)) {
182 link_type = pci_read_config32(devx, link->cap + 0x18);
183 } while(!(link_type & InitComplete));
184 if (!(link_type & NonCoherent)) {
187 /* See if there is an available configuration space mapping
188 * register in function 1.
190 ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf);
192 #if CONFIG_EXT_CONF_SUPPORT == 0
193 if(ht_c_index>=4) return max;
196 /* Set up the primary, secondary and subordinate bus numbers.
197 * We have no idea how many busses are behind this bridge yet,
198 * so we set the subordinate bus number to 0xff for the moment.
200 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
201 // first chain will on bus 0
202 if((nodeid == 0) && (sblink==link_num)) { // actually max is 0 here
205 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
206 // second chain will be on 0x40, third 0x80, forth 0xc0
207 // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0
208 // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config.
210 min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same
212 max = min_bus | (segn<<8);
222 max_bus = 0xfc | (segn<<8);
224 link->secondary = min_bus;
225 link->subordinate = max_bus;
227 /* Read the existing primary/secondary/subordinate bus
228 * number configuration.
230 busses = pci_read_config32(devx, link->cap + 0x14);
232 /* Configure the bus numbers for this bridge: the configuration
233 * transactions will not be propagates by the bridge if it is
234 * not correctly configured
236 busses &= 0xffff00ff;
237 busses |= ((u32)(link->secondary) << 8);
238 pci_write_config32(devx, link->cap + 0x14, busses);
241 /* set the config map space */
243 set_config_map_reg(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes);
245 /* Now we can scan all of the subordinate busses i.e. the
246 * chain on the hypertranport link
249 ht_unitid_base[i] = 0x20;
252 //if ext conf is enabled, only need use 0x1f
254 max_devfn = (0x17<<3) | 7;
256 max_devfn = (0x1f<<3) | 7;
258 max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid);
260 /* We know the number of busses behind this bridge. Set the
261 * subordinate bus number to it's real value
263 if(ht_c_index>3) { // clear the extend reg
264 clear_config_map_reg(nodeid, link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes);
267 link->subordinate = max;
268 set_config_map_reg(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes);
272 // use ht_unitid_base to update hcdn_reg
275 temp |= (ht_unitid_base[i] & 0xff) << (i*8);
278 sysconf.hcdn_reg[ht_c_index] = temp;
281 store_ht_c_conf_bus(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, &sysconf);
285 static unsigned amdfam10_scan_chains(device_t dev, unsigned max)
289 unsigned sblink = sysconf.sblk;
290 unsigned offset_unitid = 0;
292 nodeid = amdfam10_nodeid(dev);
294 // Put sb chain in bus 0
295 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
297 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
300 for (link = dev->link_list; link; link = link->next)
301 if (link->link_num == sblink)
302 max = amdfam10_scan_chain(dev, nodeid, link, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
306 #if CONFIG_PCI_BUS_SEGN_BITS
307 max = check_segn(dev, max, sysconf.nodes, &sysconf);
310 for(link = dev->link_list; link; link = link->next) {
311 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
312 if( (nodeid == 0) && (sblink == link->link_num) ) continue; //already done
315 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
316 #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
317 if((nodeid == 0) && (sblink == link->link_num))
322 max = amdfam10_scan_chain(dev, nodeid, link, link->link_num, sblink, max, offset_unitid);
328 static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
331 struct resource *res;
332 unsigned nodeid, link = 0;
335 for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
337 dev = __f0_dev[nodeid];
340 for(link = 0; !res && (link < 8); link++) {
341 res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
347 if ( (goal_link == (link - 1)) &&
348 (goal_nodeid == (nodeid - 1)) &&
356 static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link)
358 struct resource *resource;
362 for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
364 result = reg_useable(reg, dev, nodeid, link);
366 /* I have been allocated this one */
369 else if (result > 1) {
370 /* I have a free register pair */
375 reg = free_reg; // if no free, the free_reg still be 0
380 //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range
381 u32 index = get_io_addr_index(nodeid, link);
382 reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255
385 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
390 static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link)
392 struct resource *resource;
396 for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
398 result = reg_useable(reg, dev, nodeid, link);
400 /* I have been allocated this one */
403 else if (result > 1) {
404 /* I have a free register pair */
414 //because of Extend conf space, we will never run out of reg,
415 // but we need one index to differ them. so same node and
416 // same link can have multi range
417 u32 index = get_mmio_addr_index(nodeid, link);
418 reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63
421 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
426 static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
428 struct resource *resource;
430 /* Initialize the io space constraints on the current bus */
431 resource = amdfam10_find_iopair(dev, nodeid, link);
434 #if CONFIG_EXT_CONF_SUPPORT == 1
435 if((resource->index & 0x1fff) == 0x1110) { // ext
440 align = log2(HT_IO_HOST_ALIGN);
443 resource->align = align;
444 resource->gran = align;
445 resource->limit = 0xffffUL;
446 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
449 /* Initialize the prefetchable memory constraints on the current bus */
450 resource = amdfam10_find_mempair(dev, nodeid, link);
454 resource->align = log2(HT_MEM_HOST_ALIGN);
455 resource->gran = log2(HT_MEM_HOST_ALIGN);
456 resource->limit = 0xffffffffffULL;
457 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
458 resource->flags |= IORESOURCE_BRIDGE;
460 #if CONFIG_EXT_CONF_SUPPORT == 1
461 if((resource->index & 0x1fff) == 0x1110) { // ext
462 normalize_resource(resource);
468 /* Initialize the memory constraints on the current bus */
469 resource = amdfam10_find_mempair(dev, nodeid, link);
473 resource->align = log2(HT_MEM_HOST_ALIGN);
474 resource->gran = log2(HT_MEM_HOST_ALIGN);
475 resource->limit = 0xffffffffffULL;
476 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
477 #if CONFIG_EXT_CONF_SUPPORT == 1
478 if((resource->index & 0x1fff) == 0x1110) { // ext
479 normalize_resource(resource);
485 static void amdfam10_read_resources(device_t dev)
489 nodeid = amdfam10_nodeid(dev);
490 for(link = dev->link_list; link; link = link->next) {
491 if (link->children) {
492 amdfam10_link_read_bases(dev, nodeid, link->link_num);
497 static void amdfam10_set_resource(device_t dev, struct resource *resource,
500 resource_t rbase, rend;
501 unsigned reg, link_num;
504 /* Make certain the resource has actually been set */
505 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
509 /* If I have already stored this resource don't worry about it */
510 if (resource->flags & IORESOURCE_STORED) {
514 /* Only handle PCI memory and IO resources */
515 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
518 /* Ensure I am actually looking at a resource of function 1 */
519 if ((resource->index & 0xffff) < 0x1000) {
522 /* Get the base address */
523 rbase = resource->base;
525 /* Get the limit (rounded up) */
526 rend = resource_end(resource);
528 /* Get the register and link */
529 reg = resource->index & 0xfff; // 4k
530 link_num = IOINDEX_LINK(resource->index);
532 if (resource->flags & IORESOURCE_IO) {
534 set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
535 store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8);
537 else if (resource->flags & IORESOURCE_MEM) {
538 set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8]
539 store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8);
541 resource->flags |= IORESOURCE_STORED;
542 sprintf(buf, " <node %x link %x>",
544 report_resource_stored(dev, resource, buf);
549 * I tried to reuse the resource allocation code in amdfam10_set_resource()
550 * but it is too diffcult to deal with the resource allocation magic.
552 #if CONFIG_CONSOLE_VGA_MULTI == 1
553 extern device_t vga_pri; // the primary vga device, defined in device.c
556 static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
560 /* find out which link the VGA card is connected,
561 * we only deal with the 'first' vga card */
562 for (link = dev->link_list; link; link = link->next) {
563 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
564 #if CONFIG_CONSOLE_VGA_MULTI == 1
565 printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
566 link->secondary,link->subordinate);
567 /* We need to make sure the vga_pri is under the link */
568 if((vga_pri->bus->secondary >= link->secondary ) &&
569 (vga_pri->bus->secondary <= link->subordinate )
576 /* no VGA card installed */
580 printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
581 set_vga_enable_reg(nodeid, link->link_num);
584 static void amdfam10_set_resources(device_t dev)
588 struct resource *res;
590 /* Find the nodeid */
591 nodeid = amdfam10_nodeid(dev);
593 amdfam10_create_vga_resource(dev, nodeid);
595 /* Set each resource we have found */
596 for(res = dev->resource_list; res; res = res->next) {
597 amdfam10_set_resource(dev, res, nodeid);
600 for(bus = dev->link_list; bus; bus = bus->next) {
602 assign_resources(bus);
607 static void mcf0_control_init(struct device *dev)
611 static struct device_operations northbridge_operations = {
612 .read_resources = amdfam10_read_resources,
613 .set_resources = amdfam10_set_resources,
614 .enable_resources = pci_dev_enable_resources,
615 .init = mcf0_control_init,
616 .scan_bus = amdfam10_scan_chains,
622 static const struct pci_driver mcf0_driver __pci_driver = {
623 .ops = &northbridge_operations,
624 .vendor = PCI_VENDOR_ID_AMD,
628 struct chip_operations northbridge_amd_amdfam10_ops = {
629 CHIP_NAME("AMD FAM10 Northbridge")
633 static void amdfam10_domain_read_resources(device_t dev)
637 /* Find the already assigned resource pairs */
639 for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
641 base = f1_read_config32(reg);
642 limit = f1_read_config32(reg + 0x04);
643 /* Is this register allocated? */
644 if ((base & 3) != 0) {
645 unsigned nodeid, reg_link;
647 if(reg<0xc0) { // mmio
648 nodeid = (limit & 0xf) + (base&0x30);
650 nodeid = (limit & 0xf) + ((base>>4)&0x30);
652 reg_link = (limit >> 4) & 7;
653 reg_dev = __f0_dev[nodeid];
655 /* Reserve the resource */
656 struct resource *res;
657 res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
664 /* FIXME: do we need to check extend conf space?
665 I don't believe that much preset value */
667 #if CONFIG_PCI_64BIT_PREF_MEM == 0
668 pci_domain_read_resources(dev);
671 struct resource *resource;
672 for(link=dev->link_list; link; link = link->next) {
673 /* Initialize the system wide io space constraints */
674 resource = new_resource(dev, 0|(link->link_num<<2));
675 resource->base = 0x400;
676 resource->limit = 0xffffUL;
677 resource->flags = IORESOURCE_IO;
679 /* Initialize the system wide prefetchable memory resources constraints */
680 resource = new_resource(dev, 1|(link->link_num<<2));
681 resource->limit = 0xfcffffffffULL;
682 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
684 /* Initialize the system wide memory resources constraints */
685 resource = new_resource(dev, 2|(link->link_num<<2));
686 resource->limit = 0xfcffffffffULL;
687 resource->flags = IORESOURCE_MEM;
692 static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
694 struct resource *min;
696 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
697 if (min && tolm > min->base) {
703 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
705 struct hw_mem_hole_info {
706 unsigned hole_startk;
710 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
712 struct hw_mem_hole_info mem_hole;
715 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
716 mem_hole.node_id = -1;
718 for (i = 0; i < sysconf.nodes; i++) {
719 struct dram_base_mask_t d;
721 d = get_dram_base_mask(i);
722 if(!(d.mask & 1)) continue; // no memory on this node
724 hole = pci_read_config32(__f1_dev[i], 0xf0);
725 if(hole & 1) { // we find the hole
726 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
727 mem_hole.node_id = i; // record the node No with hole
728 break; // only one hole
732 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
733 if(mem_hole.node_id==-1) {
734 resource_t limitk_pri = 0;
735 for(i=0; i<sysconf.nodes; i++) {
736 struct dram_base_mask_t d;
737 resource_t base_k, limit_k;
738 d = get_dram_base_mask(i);
739 if(!(d.base & 1)) continue;
741 base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
742 if(base_k > 4 *1024 * 1024) break; // don't need to go to check
743 if(limitk_pri != base_k) { // we find the hole
744 mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
745 mem_hole.node_id = i;
746 break; //only one hole
749 limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
750 limitk_pri = limit_k;
756 // WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards.
757 // Does it make sense not to?
758 #if CONFIG_AMDMCT == 0
759 static void disable_hoist_memory(unsigned long hole_startk, int node_id)
763 struct dram_base_mask_t d;
770 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
771 struct mem_info *meminfo;
772 meminfo = &sysinfox->meminfo[node_id];
774 one_DCT = get_one_DCT(meminfo);
776 // 1. find which node has hole
777 // 2. change limit in that node.
778 // 3. change base and limit in later node
779 // 4. clear that node f0
781 // if there is not mem hole enabled, we need to change it's base instead
783 hole_sizek = (4*1024*1024) - hole_startk;
785 for(i=NODE_NUMS-1;i>node_id;i--) {
787 d = get_dram_base_mask(i);
789 if(!(d.mask & 1)) continue;
791 d.base -= (hole_sizek>>9);
792 d.mask -= (hole_sizek>>9);
793 set_dram_base_mask(i, d, sysconf.nodes);
795 if(get_DctSelHiEn(i) & 1) {
796 sel_m = get_DctSelBaseAddr(i);
797 sel_m -= hole_startk>>10;
798 set_DctSelBaseAddr(i, sel_m);
802 d = get_dram_base_mask(node_id);
803 dev = __f1_dev[node_id];
804 sel_hi_en = get_DctSelHiEn(node_id);
807 sel_m = get_DctSelBaseAddr(node_id);
809 hoist = pci_read_config32(dev, 0xf0);
811 pci_write_config32(dev, 0xf0, 0);
812 d.mask -= (hole_sizek>>9);
813 set_dram_base_mask(node_id, d, sysconf.nodes);
814 if(one_DCT || (sel_m >= (hole_startk>>10))) {
816 sel_m -= hole_startk>>10;
817 set_DctSelBaseAddr(node_id, sel_m);
821 set_DctSelBaseOffset(node_id, 0);
824 d.base -= (hole_sizek>>9);
825 d.mask -= (hole_sizek>>9);
826 set_dram_base_mask(node_id, d, sysconf.nodes);
829 sel_m -= hole_startk>>10;
830 set_DctSelBaseAddr(node_id, sel_m);
839 #if CONFIG_WRITE_HIGH_TABLES==1
840 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
841 extern uint64_t high_tables_base, high_tables_size;
844 #if CONFIG_GFXUMA == 1
845 extern uint64_t uma_memory_base, uma_memory_size;
847 static void add_uma_resource(struct device *dev, int index)
849 struct resource *resource;
851 printk(BIOS_DEBUG, "Adding UMA memory area\n");
852 resource = new_resource(dev, index);
853 resource->base = (resource_t) uma_memory_base;
854 resource->size = (resource_t) uma_memory_size;
855 resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
856 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
860 static void amdfam10_domain_set_resources(device_t dev)
862 #if CONFIG_PCI_64BIT_PREF_MEM == 1
863 struct resource *io, *mem1, *mem2;
864 struct resource *res;
866 unsigned long mmio_basek;
870 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
871 struct hw_mem_hole_info mem_hole;
872 u32 reset_memhole = 1;
875 #if CONFIG_PCI_64BIT_PREF_MEM == 1
877 for(link = dev->link_list; link; link = link->next) {
878 /* Now reallocate the pci resources memory with the
879 * highest addresses I can manage.
881 mem1 = find_resource(dev, 1|(link->link_num<<2));
882 mem2 = find_resource(dev, 2|(link->link_num<<2));
884 printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
885 mem1->base, mem1->limit, mem1->size, mem1->align);
886 printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
887 mem2->base, mem2->limit, mem2->size, mem2->align);
889 /* See if both resources have roughly the same limits */
890 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
891 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
893 /* If so place the one with the most stringent alignment first
895 if (mem2->align > mem1->align) {
896 struct resource *tmp;
901 /* Now place the memory as high up as it will go */
902 mem2->base = resource_max(mem2);
903 mem1->limit = mem2->base - 1;
904 mem1->base = resource_max(mem1);
907 /* Place the resources as high up as they will go */
908 mem2->base = resource_max(mem2);
909 mem1->base = resource_max(mem1);
912 printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
913 mem1->base, mem1->limit, mem1->size, mem1->align);
914 printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
915 mem2->base, mem2->limit, mem2->size, mem2->align);
918 for(res = &dev->resource_list; res; res = res->next)
920 res->flags |= IORESOURCE_ASSIGNED;
921 res->flags |= IORESOURCE_STORED;
922 report_resource_stored(dev, res, "");
926 pci_tolm = 0xffffffffUL;
927 for(link = dev->link_list; link; link = link->next) {
928 pci_tolm = my_find_pci_tolm(link, pci_tolm);
931 // FIXME handle interleaved nodes. If you fix this here, please fix
933 mmio_basek = pci_tolm >> 10;
934 /* Round mmio_basek to something the processor can support */
935 mmio_basek &= ~((1 << 6) -1);
937 // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
938 // MMIO hole. If you fix this here, please fix amdk8, too.
939 /* Round the mmio hole to 64M */
940 mmio_basek &= ~((64*1024) - 1);
942 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
943 /* if the hw mem hole is already set in raminit stage, here we will compare
944 * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
945 * use hole_basek as mmio_basek and we don't need to reset hole.
946 * otherwise We reset the hole to the mmio_basek
949 mem_hole = get_hw_mem_hole_info();
951 // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
952 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
953 mmio_basek = mem_hole.hole_startk;
957 #if CONFIG_AMDMCT == 0
958 //mmio_basek = 3*1024*1024; // for debug to meet boundary
961 if(mem_hole.node_id!=-1) {
962 /* We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not
963 make hole_startk to some basek too!
964 We need to reset our Mem Hole, because We want more big HOLE
966 Before that We need to disable mem hole at first, becase
967 memhole could already be set on i+1 instead
969 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
972 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
973 // We need to double check if the mmio_basek is valid for hole
974 // setting, if it is equal to basek, we need to decrease it some
975 resource_t basek_pri;
976 for (i = 0; i < sysconf.nodes; i++) {
977 struct dram_base_mask_t d;
979 d = get_dram_base_mask(i);
981 if(!(d.mask &1)) continue;
983 basek = ((resource_t)(d.base & 0x1fffff00)) << 9;
984 if(mmio_basek == (u32)basek) {
985 mmio_basek -= (uin32_t)(basek - basek_pri); // increase mem hole size to make sure it is on middle of pri node
998 for(i = 0; i < sysconf.nodes; i++) {
999 struct dram_base_mask_t d;
1000 resource_t basek, limitk, sizek; // 4 1T
1001 d = get_dram_base_mask(i);
1003 if(!(d.mask & 1)) continue;
1004 basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
1005 limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ;
1006 sizek = limitk - basek;
1008 /* see if we need a hole from 0xa0000 to 0xbffff */
1009 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
1010 ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
1012 basek = (8*64)+(16*16);
1013 sizek = limitk - ((8*64)+(16*16));
1017 // printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk);
1019 /* split the region to accomodate pci memory space */
1020 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1021 if (basek <= mmio_basek) {
1023 pre_sizek = mmio_basek - basek;
1025 ram_resource(dev, (idx | i), basek, pre_sizek);
1028 #if CONFIG_WRITE_HIGH_TABLES==1
1029 if (high_tables_base==0) {
1030 /* Leave some space for ACPI, PIRQ and MP tables */
1031 #if CONFIG_GFXUMA == 1
1032 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
1034 high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
1036 high_tables_size = HIGH_TABLES_SIZE * 1024;
1037 printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
1042 #if CONFIG_AMDMCT == 0
1043 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1045 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
1046 struct mem_info *meminfo;
1047 meminfo = &sysinfox->meminfo[i];
1048 sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes);
1055 if ((basek + sizek) <= 4*1024*1024) {
1059 basek = 4*1024*1024;
1060 sizek -= (4*1024*1024 - mmio_basek);
1064 #if CONFIG_GFXUMA == 1
1065 /* Deduct uma memory before reporting because
1066 * this is what the mtrr code expects */
1067 sizek -= uma_memory_size / 1024;
1069 ram_resource(dev, (idx | i), basek, sizek);
1071 #if CONFIG_WRITE_HIGH_TABLES==1
1072 printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
1073 i, mmio_basek, basek, limitk);
1074 if (high_tables_base==0) {
1075 /* Leave some space for ACPI, PIRQ and MP tables */
1076 #if CONFIG_GFXUMA == 1
1077 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
1079 high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
1081 high_tables_size = HIGH_TABLES_SIZE * 1024;
1086 #if CONFIG_GFXUMA == 1
1087 add_uma_resource(dev, 7);
1090 for(link = dev->link_list; link; link = link->next) {
1091 if (link->children) {
1092 assign_resources(link);
1097 static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
1102 /* Unmap all of the HT chains */
1103 for(reg = 0xe0; reg <= 0xec; reg += 4) {
1104 f1_write_config32(reg, 0);
1106 #if CONFIG_EXT_CONF_SUPPORT == 1
1108 for(i = 0; i< sysconf.nodes; i++) {
1110 for(index = 0; index < 64; index++) {
1111 pci_write_config32(__f1_dev[i], 0x110, index | (6<<28));
1112 pci_write_config32(__f1_dev[i], 0x114, 0);
1119 for(link = dev->link_list; link; link = link->next) {
1120 max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max);
1123 /* Tune the hypertransport transaction for best performance.
1124 * Including enabling relaxed ordering if it is safe.
1127 for(i = 0; i < fx_devs; i++) {
1129 f0_dev = __f0_dev[i];
1130 if (f0_dev && f0_dev->enabled) {
1132 httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1133 httc &= ~HTTC_RSP_PASS_PW;
1134 if (!dev->link_list->disable_relaxed_ordering) {
1135 httc |= HTTC_RSP_PASS_PW;
1137 printk(BIOS_SPEW, "%s passpw: %s\n",
1139 (!dev->link_list->disable_relaxed_ordering)?
1140 "enabled":"disabled");
1141 pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1147 static struct device_operations pci_domain_ops = {
1148 .read_resources = amdfam10_domain_read_resources,
1149 .set_resources = amdfam10_domain_set_resources,
1150 .enable_resources = NULL,
1152 .scan_bus = amdfam10_domain_scan_bus,
1153 #if CONFIG_MMCONF_SUPPORT_DEFAULT
1154 .ops_pci_bus = &pci_ops_mmconf,
1156 .ops_pci_bus = &pci_cf8_conf1,
1160 static void sysconf_init(device_t dev) // first node
1162 sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
1164 sysconf.ht_c_num = 0;
1166 unsigned ht_c_index;
1168 for(ht_c_index=0; ht_c_index<32; ht_c_index++) {
1169 sysconf.ht_c_conf_bus[ht_c_index] = 0;
1172 sysconf.nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1;
1173 #if CONFIG_MAX_PHYSICAL_CPUS > 8
1174 sysconf.nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3);
1177 sysconf.enabled_apic_ext_id = 0;
1178 sysconf.lift_bsp_apicid = 0;
1180 /* Find the bootstrap processors apicid */
1181 sysconf.bsp_apicid = lapicid();
1182 sysconf.apicid_offset = sysconf.bsp_apicid;
1184 #if (CONFIG_ENABLE_APIC_EXT_ID == 1)
1185 if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1187 sysconf.enabled_apic_ext_id = 1;
1189 #if (CONFIG_APIC_ID_OFFSET>0)
1190 if(sysconf.enabled_apic_ext_id) {
1191 if(sysconf.bsp_apicid == 0) {
1192 /* bsp apic id is not changed */
1193 sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
1195 sysconf.lift_bsp_apicid = 1;
1202 static void add_more_links(device_t dev, unsigned total_links)
1204 struct bus *link, *last = NULL;
1207 for (link = dev->link_list; link; link = link->next)
1211 int links = total_links - last->link_num;
1212 link_num = last->link_num;
1214 link = malloc(links*sizeof(*link));
1216 die("Couldn't allocate more links!\n");
1217 memset(link, 0, links*sizeof(*link));
1223 link = malloc(total_links*sizeof(*link));
1224 memset(link, 0, total_links*sizeof(*link));
1225 dev->link_list = link;
1228 for (link_num = link_num + 1; link_num < total_links; link_num++) {
1229 link->link_num = link_num;
1231 link->next = link + 1;
1238 static u32 cpu_bus_scan(device_t dev, u32 max)
1240 struct bus *cpu_bus;
1243 device_t pci_domain;
1250 int disable_siblings;
1251 unsigned ApicIdCoreIdSize;
1254 ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
1255 if(ApicIdCoreIdSize) {
1256 siblings = (1<<ApicIdCoreIdSize)-1;
1258 siblings = 3; //quad core
1261 disable_siblings = !CONFIG_LOGICAL_CPUS;
1262 #if CONFIG_LOGICAL_CPUS == 1
1263 get_option(&disable_siblings, "multi_core");
1266 // How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp???
1267 nb_cfg_54 = read_nb_cfg_54();
1270 dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
1271 if(dev_mc && dev_mc->bus) {
1272 printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
1273 pci_domain = dev_mc->bus->dev;
1274 if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
1275 printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
1276 dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
1277 printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
1280 printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
1282 printk(BIOS_DEBUG, "\n");
1284 dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
1286 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1287 if (dev_mc && dev_mc->bus) {
1288 printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
1289 pci_domain = dev_mc->bus->dev;
1290 if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
1291 if((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
1292 printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
1293 dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
1294 printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
1296 printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
1297 dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
1298 printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
1299 dev_mc = dev_mc->sibling;
1308 dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
1310 printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
1314 sysconf_init(dev_mc);
1316 nodes = sysconf.nodes;
1318 #if CONFIG_CBB && (NODE_NUMS > 32)
1319 if(nodes>32) { // need to put node 32 to node 63 to bus 0xfe
1320 if(pci_domain->link_list && !pci_domain->link_list->next) {
1321 struct bus *new_link = new_link(pci_domain);
1322 pci_domain->link_list->next = new_link;
1323 new_link->link_num = 1;
1324 new_link->dev = pci_domain;
1325 new_link->children = 0;
1326 printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain));
1328 pci_domain->link_list->next->secondary = CONFIG_CBB - 1;
1331 /* Find which cpus are present */
1332 cpu_bus = dev->link_list;
1333 for(i = 0; i < nodes; i++) {
1334 device_t cdb_dev, cpu;
1335 struct device_path cpu_path;
1336 unsigned busn, devn;
1340 devn = CONFIG_CDB+i;
1342 #if CONFIG_CBB && (NODE_NUMS > 32)
1346 pbus = pci_domain->link_list->next);
1350 /* Find the cpu's pci device */
1351 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
1353 /* If I am probing things in a weird order
1354 * ensure all of the cpu's pci devices are found.
1357 for(fn = 0; fn <= 5; fn++) { //FBDIMM?
1358 cdb_dev = pci_probe_dev(NULL, pbus,
1359 PCI_DEVFN(devn, fn));
1361 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
1364 /* Ok, We need to set the links for that device.
1365 * otherwise the device under it will not be scanned
1368 #if CONFIG_HT3_SUPPORT==1
1373 add_more_links(cdb_dev, linknum);
1376 cores_found = 0; // one core
1377 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
1378 if (cdb_dev && cdb_dev->enabled) {
1379 j = pci_read_config32(cdb_dev, 0xe8);
1380 cores_found = (j >> 12) & 3; // dev is func 3
1382 cores_found |= (j >> 13) & 4;
1383 printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cdb_dev), cores_found);
1387 if(disable_siblings) {
1394 for (j = 0; j <=jj; j++ ) {
1396 /* Build the cpu device path */
1397 cpu_path.type = DEVICE_PATH_APIC;
1398 cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ?
1400 /* See if I can find the cpu */
1401 cpu = find_dev_path(cpu_bus, &cpu_path);
1403 /* Enable the cpu if I have the processor */
1404 if (cdb_dev && cdb_dev->enabled) {
1406 cpu = alloc_dev(cpu_bus, &cpu_path);
1413 /* Disable the cpu if I don't have the processor */
1414 if (cpu && (!cdb_dev || !cdb_dev->enabled)) {
1418 /* Report what I have done */
1420 cpu->path.apic.node_id = i;
1421 cpu->path.apic.core_id = j;
1422 #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET>0)
1423 if(sysconf.enabled_apic_ext_id) {
1424 if(sysconf.lift_bsp_apicid) {
1425 cpu->path.apic.apic_id += sysconf.apicid_offset;
1428 if (cpu->path.apic.apic_id != 0)
1429 cpu->path.apic.apic_id += sysconf.apicid_offset;
1433 printk(BIOS_DEBUG, "CPU: %s %s\n",
1434 dev_path(cpu), cpu->enabled?"enabled":"disabled");
1442 static void cpu_bus_init(device_t dev)
1444 initialize_cpus(dev->link_list);
1447 static void cpu_bus_noop(device_t dev)
1451 static void cpu_bus_read_resources(device_t dev)
1453 #if CONFIG_MMCONF_SUPPORT
1454 struct resource *resource = new_resource(dev, 0xc0010058);
1455 resource->base = CONFIG_MMCONF_BASE_ADDRESS;
1456 resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
1457 resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
1458 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
1462 static void cpu_bus_set_resources(device_t dev)
1464 struct resource *resource = find_resource(dev, 0xc0010058);
1466 report_resource_stored(dev, resource, " <mmconfig>");
1468 pci_dev_set_resources(dev);
1471 static struct device_operations cpu_bus_ops = {
1472 .read_resources = cpu_bus_read_resources,
1473 .set_resources = cpu_bus_set_resources,
1474 .enable_resources = cpu_bus_noop,
1475 .init = cpu_bus_init,
1476 .scan_bus = cpu_bus_scan,
1479 static void root_complex_enable_dev(struct device *dev)
1481 /* Set the operations if it is a special bus type */
1482 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1483 dev->ops = &pci_domain_ops;
1485 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1486 dev->ops = &cpu_bus_ops;
1490 struct chip_operations northbridge_amd_amdfam10_root_complex_ops = {
1491 CHIP_NAME("AMD FAM10 Root Complex")
1492 .enable_dev = root_complex_enable_dev,