src/northbridge/amd/amdfam10/debug.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /*
  21  * Generic FAM10 debug code, used by mainboard specific romstage.c
  22  */
  23
  24 #include "amdfam10_pci.c"
  25
  26 static void udelay_tsc(u32 us);
  27
  28 static inline void print_debug_addr(const char *str, void *val)
  29 {
  30 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1
  31                 printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
  32 #endif
  33 }
  34
  35 static void print_debug_pci_dev(u32 dev)
  36 {
  37 #if CONFIG_PCI_BUS_SEGN_BITS==0
  38         printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
  39 #else
  40         printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
  41 #endif
  42 }
  43
  44 static inline void print_pci_devices(void)
  45 {
  46         device_t dev;
  47         for(dev = PCI_DEV(0, 0, 0);
  48                 dev <= PCI_DEV(0xff, 0x1f, 0x7);
  49                 dev += PCI_DEV(0,0,1)) {
  50                 u32 id;
  51                 id = pci_read_config32(dev, PCI_VENDOR_ID);
  52                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
  53                         (((id >> 16) & 0xffff) == 0xffff) ||
  54                         (((id >> 16) & 0xffff) == 0x0000)) {
  55                         continue;
  56                 }
  57                 print_debug_pci_dev(dev);
  58                 printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
  59                 if(((dev>>12) & 0x07) == 0) {
  60                         u8 hdr_type;
  61                         hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
  62                         if((hdr_type & 0x80) != 0x80) {
  63                                 dev += PCI_DEV(0,0,7);
  64                         }
  65                 }
  66         }
  67 }
  68
  69 static inline void print_pci_devices_on_bus(u32 busn)
  70 {
  71         device_t dev;
  72         for(dev = PCI_DEV(busn, 0, 0);
  73                 dev <= PCI_DEV(busn, 0x1f, 0x7);
  74                 dev += PCI_DEV(0,0,1)) {
  75                 u32 id;
  76                 id = pci_read_config32(dev, PCI_VENDOR_ID);
  77                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
  78                    (((id >> 16) & 0xffff) == 0xffff) ||
  79                    (((id >> 16) & 0xffff) == 0x0000)) {
  80                         continue;
  81                 }
  82                 print_debug_pci_dev(dev);
  83                 printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
  84                 if(((dev>>12) & 0x07) == 0) {
  85                         u8 hdr_type;
  86                         hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
  87                         if((hdr_type & 0x80) != 0x80) {
  88                                  dev += PCI_DEV(0,0,7);
  89                         }
  90                 }
  91         }
  92 }
  93
  94
  95
  96 static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
  97 {
  98         int i;
  99         print_debug_pci_dev(dev);
 100         int j;
 101         int end = start_reg + size;
 102
 103         for(i = start_reg; i < end; i+=4) {
 104                 u32 val;
 105                 if ((i & 0x0f) == 0) {
 106                         printk(BIOS_DEBUG, "\n%04x:",i);
 107                 }
 108                 val = pci_read_config32(dev, i);
 109                 for(j=0;j<4;j++) {
 110                         printk(BIOS_DEBUG, " %02x", val & 0xff);
 111                         val >>= 8;
 112                 }
 113         }
 114         print_debug("\n");
 115 }
 116 static void dump_pci_device(u32 dev)
 117 {
 118         dump_pci_device_range(dev, 0, 4096);
 119 }
 120 static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
 121                                         u32 size)
 122 {
 123         int i;
 124         int end = start + size;
 125         print_debug_pci_dev(dev);
 126         print_debug(" -- index_reg="); print_debug_hex32(index_reg);
 127
 128         for(i = start; i < end; i++) {
 129                 u32 val;
 130                 int j;
 131                 printk(BIOS_DEBUG, "\n%02x:",i);
 132                 val = pci_read_config32_index_wait(dev, index_reg, i);
 133                 for(j=0;j<4;j++) {
 134                         printk(BIOS_DEBUG, " %02x", val & 0xff);
 135                         val >>= 8;
 136                 }
 137
 138         }
 139         print_debug("\n");
 140 }
 141 static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg)
 142 {
 143         dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54);
 144         dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz
 145 //      dump_pci_device_index_wait_range(dev, index_reg, 0x200, 0x08); //DIMM2
 146 //      dump_pci_device_index_wait_range(dev, index_reg, 0x300, 0x08); //DIMM3
 147
 148 }
 149
 150 static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
 151 {
 152         int i;
 153         print_debug_pci_dev(dev);
 154
 155         print_debug(" index reg: "); print_debug_hex16(index_reg); print_debug(" type: "); print_debug_hex8(type);
 156
 157         type<<=28;
 158
 159         for(i = 0; i < length; i++) {
 160                 u32 val;
 161                 if ((i & 0x0f) == 0) {
 162                         printk(BIOS_DEBUG, "\n%02x:",i);
 163                 }
 164                 val = pci_read_config32_index(dev, index_reg, i|type);
 165                 printk(BIOS_DEBUG, " %08x", val);
 166         }
 167         print_debug("\n");
 168 }
 169
 170
 171 static inline void dump_pci_devices(void)
 172 {
 173         device_t dev;
 174         for(dev = PCI_DEV(0, 0, 0);
 175                 dev <= PCI_DEV(0xff, 0x1f, 0x7);
 176                 dev += PCI_DEV(0,0,1)) {
 177                 u32 id;
 178                 id = pci_read_config32(dev, PCI_VENDOR_ID);
 179                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
 180                         (((id >> 16) & 0xffff) == 0xffff) ||
 181                         (((id >> 16) & 0xffff) == 0x0000)) {
 182                         continue;
 183                 }
 184                 dump_pci_device(dev);
 185
 186                 if(((dev>>12) & 0x07) == 0) {
 187                         u8 hdr_type;
 188                         hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
 189                         if((hdr_type & 0x80) != 0x80) {
 190                                 dev += PCI_DEV(0,0,7);
 191                         }
 192                 }
 193         }
 194 }
 195
 196
 197 static inline void dump_pci_devices_on_bus(u32 busn)
 198 {
 199         device_t dev;
 200         for(dev = PCI_DEV(busn, 0, 0);
 201                 dev <= PCI_DEV(busn, 0x1f, 0x7);
 202                 dev += PCI_DEV(0,0,1)) {
 203                 u32 id;
 204                 id = pci_read_config32(dev, PCI_VENDOR_ID);
 205                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
 206                    (((id >> 16) & 0xffff) == 0xffff) ||
 207                    (((id >> 16) & 0xffff) == 0x0000)) {
 208                         continue;
 209                 }
 210                 dump_pci_device(dev);
 211
 212                 if(((dev>>12) & 0x07) == 0) {
 213                         u8 hdr_type;
 214                         hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
 215                         if((hdr_type & 0x80) != 0x80) {
 216                                 dev += PCI_DEV(0,0,7);
 217                         }
 218                 }
 219         }
 220 }
 221
 222 #if CONFIG_DEBUG_SMBUS
 223
 224 static void dump_spd_registers(const struct mem_controller *ctrl)
 225 {
 226         int i;
 227         print_debug("\n");
 228         for(i = 0; i < DIMM_SOCKETS; i++) {
 229                 u32 device;
 230                 device = ctrl->spd_addr[i];
 231                 if (device) {
 232                         int j;
 233                         printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 234                         for(j = 0; j < 128; j++) {
 235                                 int status;
 236                                 u8 byte;
 237                                 if ((j & 0xf) == 0) {
 238                                         printk(BIOS_DEBUG, "\n%02x: ", j);
 239                                 }
 240                                 status = smbus_read_byte(device, j);
 241                                 if (status < 0) {
 242                                         break;
 243                                 }
 244                                 byte = status & 0xff;
 245                                 printk(BIOS_DEBUG, "%02x ", byte);
 246                         }
 247                         print_debug("\n");
 248                 }
 249                 device = ctrl->spd_addr[i+DIMM_SOCKETS];
 250                 if (device) {
 251                         int j;
 252                         printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 253                         for(j = 0; j < 128; j++) {
 254                                 int status;
 255                                 u8 byte;
 256                                 if ((j & 0xf) == 0) {
 257                                         printk(BIOS_DEBUG, "\n%02x: ", j);
 258                                 }
 259                                 status = smbus_read_byte(device, j);
 260                                 if (status < 0) {
 261                                         break;
 262                                 }
 263                                 byte = status & 0xff;
 264                                 printk(BIOS_DEBUG, "%02x ", byte);
 265                         }
 266                         print_debug("\n");
 267                 }
 268         }
 269 }
 270 static void dump_smbus_registers(void)
 271 {
 272         u32 device;
 273         print_debug("\n");
 274         for(device = 1; device < 0x80; device++) {
 275                 int j;
 276                 if( smbus_read_byte(device, 0) < 0 ) continue;
 277                 printk(BIOS_DEBUG, "smbus: %02x", device);
 278                 for(j = 0; j < 256; j++) {
 279                         int status;
 280                         u8 byte;
 281                         status = smbus_read_byte(device, j);
 282                         if (status < 0) {
 283                                 break;
 284                         }
 285                         if ((j & 0xf) == 0) {
 286                                 printk(BIOS_DEBUG, "\n%02x: ",j);
 287                         }
 288                         byte = status & 0xff;
 289                         printk(BIOS_DEBUG, "%02x ", byte);
 290                 }
 291                 print_debug("\n");
 292         }
 293 }
 294 #endif
 295 static inline void dump_io_resources(u32 port)
 296 {
 297
 298         int i;
 299         udelay_tsc(2000);
 300         printk(BIOS_DEBUG, "%04x:\n", port);
 301         for(i=0;i<256;i++) {
 302                 u8 val;
 303                 if ((i & 0x0f) == 0) {
 304                         printk(BIOS_DEBUG, "%02x:", i);
 305                 }
 306                 val = inb(port);
 307                 printk(BIOS_DEBUG, " %02x",val);
 308                 if ((i & 0x0f) == 0x0f) {
 309                         print_debug("\n");
 310                 }
 311                 port++;
 312         }
 313 }
 314
 315 static inline void dump_mem(u32 start, u32 end)
 316 {
 317         u32 i;
 318         print_debug("dump_mem:");
 319         for(i=start;i<end;i++) {
 320                 if((i & 0xf)==0) {
 321                         printk(BIOS_DEBUG, "\n%08x:", i);
 322                 }
 323                 printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 324         }
 325         print_debug("\n");
 326 }