2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 /* Definitions of various FAM10 registers */
25 #define HT_TRANSACTION_CONTROL 0x68
26 #define HTTC_DIS_RD_B_P (1 << 0)
27 #define HTTC_DIS_RD_DW_P (1 << 1)
28 #define HTTC_DIS_WR_B_P (1 << 2)
29 #define HTTC_DIS_WR_DW_P (1 << 3)
30 #define HTTC_DIS_MTS (1 << 4)
31 #define HTTC_CPU1_EN (1 << 5)
32 #define HTTC_CPU_REQ_PASS_PW (1 << 6)
33 #define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
34 #define HTTC_DIS_P_MEM_C (1 << 8)
35 #define HTTC_DIS_RMT_MEM_C (1 << 9)
36 #define HTTC_DIS_FILL_P (1 << 10)
37 #define HTTC_RSP_PASS_PW (1 << 11)
38 #define HTTC_BUF_REL_PRI_SHIFT 13
39 #define HTTC_BUF_REL_PRI_MASK 3
40 #define HTTC_BUF_REL_PRI_64 0
41 #define HTTC_BUF_REL_PRI_16 1
42 #define HTTC_BUF_REL_PRI_8 2
43 #define HTTC_BUF_REL_PRI_2 3
44 #define HTTC_LIMIT_CLDT_CFG (1 << 15)
45 #define HTTC_LINT_EN (1 << 16)
46 #define HTTC_APIC_EXT_BRD_CST (1 << 17)
47 #define HTTC_APIC_EXT_ID (1 << 18)
48 #define HTTC_APIC_EXT_SPUR (1 << 19)
49 #define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
50 #define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
51 #define HTTC_DS_NP_REQ_LIMIT_MASK 3
52 #define HTTC_DS_NP_REQ_LIMIT_NONE 0
53 #define HTTC_DS_NP_REQ_LIMIT_1 1
54 #define HTTC_DS_NP_REQ_LIMIT_4 2
55 #define HTTC_DS_NP_REQ_LIMIT_8 3
59 #define PCI_IO_BASE0 0xc0
60 #define PCI_IO_BASE1 0xc8
61 #define PCI_IO_BASE2 0xd0
62 #define PCI_IO_BASE3 0xd8
63 #define PCI_IO_BASE_VGA_EN (1 << 4)
64 #define PCI_IO_BASE_NO_ISA (1 << 5)
68 #define DRAM_CSBASE 0x40
69 #define DRAM_CSMASK 0x60
70 #define DRAM_BANK_ADDR_MAP 0x80
72 #define DRAM_CTRL 0x78
73 #define DC_RdPtrInit_SHIFT 0
74 #define DC_RdPrtInit_MASK 0xf
75 #define DC_Twrrd3_2_SHIFT 8 /*DDR3 */
76 #define DC_Twrrd3_2_MASK 3
77 #define DC_Twrwr3_2_SHIFT 10 /*DDR3 */
78 #define DC_Twrwr3_2_MASK 3
79 #define DC_Trdrd3_2_SHIFT 12 /*DDR3 */
80 #define DC_Trdrd3_2_MASK 3
81 #define DC_AltVidC3MemClkTriEn (1<<16)
82 #define DC_DqsRcvEnTrain (1<<18)
83 #define DC_MaxRdLatency_SHIFT 22
84 #define DC_MaxRdLatency_MASK 0x3ff
86 #define DRAM_INIT 0x7c
87 #define DI_MrsAddress_SHIFT 0
88 #define DI_MrsAddress_MASK 0xffff
89 #define DI_MrsBank_SHIFT 16
90 #define DI_MrsBank_MASK 7
91 #define DI_MrsChipSel_SHIFT 20
92 #define DI_MrsChipSel_MASK 7
93 #define DI_SendRchgAll (1<<24)
94 #define DI_SendAutoRefresh (1<<25)
95 #define DI_SendMrsCmd (1<<26)
96 #define DI_DeassertMemRstX (1<<27)
97 #define DI_AssertCke (1<<28)
98 #define DI_SendZQCmd (1<<29) /*DDR3 */
99 #define DI_EnMrsCmd (1<<30)
100 #define DI_EnDramInit (1<<31)
102 #define DRAM_MRS 0x84
103 #define DM_BurstCtrl_SHIFT 0
104 #define DM_BurstCtrl_MASK 3
105 #define DM_DrvImpCtrl_SHIFT 2 /* DDR3 */
106 #define DM_DrvImpCtrl_MASK 3
107 #define DM_Twr_SHIFT 4 /* DDR3 */
108 #define DM_Twr_MASK 7
109 #define DM_Twr_BASE 4
111 #define DM_Twr_MAX 12
112 #define DM_DramTerm_SHIFT 7 /*DDR3 */
113 #define DM_DramTerm_MASK 7
114 #define DM_DramTermDyn_SHIFT 10 /* DDR3 */
115 #define DM_DramTermDyn_MASK 3
116 #define DM_Ooff (1<<13)
117 #define DM_ASR (1<<18)
118 #define DM_SRT (1<<19)
119 #define DM_Tcwl_SHIFT 20
120 #define DM_Tcwl_MASK 7
121 #define DM_PchgPDModeSel (1<<23) /* DDR3 */
122 #define DM_MPrLoc_SHIFT 24 /* DDR3 */
123 #define DM_MPrLoc_MASK 3
124 #define DM_MprEn (1<<26) /* DDR3 */
126 #define DRAM_TIMING_LOW 0x88
127 #define DTL_TCL_SHIFT 0
128 #define DTL_TCL_MASK 0xf
129 #define DTL_TCL_BASE 1 /* DDR3 =4 */
130 #define DTL_TCL_MIN 3 /* DDR3 =4 */
131 #define DTL_TCL_MAX 6 /* DDR3 =12 */
132 #define DTL_TRCD_SHIFT 4
133 #define DTL_TRCD_MASK 3 /* DDR3 =7 */
134 #define DTL_TRCD_BASE 3 /* DDR3 =5 */
135 #define DTL_TRCD_MIN 3 /* DDR3 =5 */
136 #define DTL_TRCD_MAX 6 /* DDR3 =12 */
137 #define DTL_TRP_SHIFT 8 /* DDR3 =7 */
138 #define DTL_TRP_MASK 3 /* DDR3 =7 */
139 #define DTL_TRP_BASE 3 /* DDR3 =5 */
140 #define DTL_TRP_MIN 3 /* DDR3 =5 */
141 #define DTL_TRP_MAX 6 /* DDR3 =12 */
142 #define DTL_TRTP_SHIFT 11 /*DDR3 =10 */
143 #define DTL_TRTP_MASK 1 /*DDR3 =3 */
144 #define DTL_TRTP_BASE 2 /* DDR3 =4 */
145 #define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ /* DDR3 =4 for 32bytes or 64bytes */
146 #define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ /* DDR3 =7 for 32Bytes or 64bytes */
147 #define DTL_TRAS_SHIFT 12
148 #define DTL_TRAS_MASK 0xf
149 #define DTL_TRAS_BASE 3 /* DDR3 =15 */
150 #define DTL_TRAS_MIN 5 /* DDR3 =15 */
151 #define DTL_TRAS_MAX 18 /*DDR3 =30 */
152 #define DTL_TRC_SHIFT 16
153 #define DTL_TRC_MASK 0xf /* DDR3 =0x1f */
154 #define DTL_TRC_BASE 11
155 #define DTL_TRC_MIN 11
156 #define DTL_TRC_MAX 26 /* DDR3 =43 */
157 #define DTL_TWR_SHIFT 20 /* only for DDR2, DDR3's is on DC */
158 #define DTL_TWR_MASK 3
159 #define DTL_TWR_BASE 3
160 #define DTL_TWR_MIN 3
161 #define DTL_TWR_MAX 6
162 #define DTL_TRRD_SHIFT 22
163 #define DTL_TRRD_MASK 3
164 #define DTL_TRRD_BASE 2 /* DDR3 =4 */
165 #define DTL_TRRD_MIN 2 /* DDR3 =4 */
166 #define DTL_TRRD_MAX 5 /* DDR3 =7 */
167 #define DTL_MemClkDis_SHIFT 24 /* Channel A */
168 #define DTL_MemClkDis3 (1 << 26)
169 #define DTL_MemClkDis2 (1 << 27)
170 #define DTL_MemClkDis1 (1 << 28)
171 #define DTL_MemClkDis0 (1 << 29)
172 /* DTL_MemClkDis for m2 and s1g1 is different */
174 #define DRAM_TIMING_HIGH 0x8c
175 #define DTH_TRWTWB_SHIFT 0
176 #define DTH_TRWTWB_MASK 3
177 #define DTH_TRWTWB_BASE 3 /* DDR3 =4 */
178 #define DTH_TRWTWB_MIN 3 /* DDR3 =5 */
179 #define DTH_TRWTWB_MAX 10 /* DDR3 =11 */
180 #define DTH_TRWTTO_SHIFT 4
181 #define DTH_TRWTTO_MASK 7
182 #define DTH_TRWTTO_BASE 2 /* DDR3 =3 */
183 #define DTH_TRWTTO_MIN 2 /* DDR3 =3 */
184 #define DTH_TRWTTO_MAX 9 /* DDR3 =10 */
185 #define DTH_TWTR_SHIFT 8
186 #define DTH_TWTR_MASK 3
187 #define DTH_TWTR_BASE 0 /* DDR3 =4 */
188 #define DTH_TWTR_MIN 1 /* DDR3 =4 */
189 #define DTH_TWTR_MAX 3 /* DDR3 =7 */
190 #define DTH_TWRRD_SHIFT 10
191 #define DTH_TWRRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */
192 #define DTH_TWRRD_BASE 0 /* DDR3 =0 */
193 #define DTH_TWRRD_MIN 0 /* DDR3 =2 */
194 #define DTH_TWRRD_MAX 3 /* DDR3 =12 */
195 #define DTH_TWRWR_SHIFT 12
196 #define DTH_TWRWR_MASK 3 /* For DDR3 3_2 is at 0x78 DC */
197 #define DTH_TWRWR_BASE 1
198 #define DTH_TWRWR_MIN 1 /* DDR3 =3 */
199 #define DTH_TWRWR_MAX 3 /* DDR3 =12 */
200 #define DTH_TRDRD_SHIFT 14
201 #define DTH_TRDRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */
202 #define DTH_TRDRD_BASE 2
203 #define DTH_TRDRD_MIN 2
204 #define DTH_TRDRD_MAX 5 /* DDR3 =10 */
205 #define DTH_TREF_SHIFT 16
206 #define DTH_TREF_MASK 3
207 #define DTH_TREF_7_8_US 2
208 #define DTH_TREF_3_9_US 3
209 #define DTH_DisAutoRefresh (1<<18)
210 #define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */
211 #define DTH_TRFC_MASK 7
212 #define DTH_TRFC_75_256M 0
213 #define DTH_TRFC_105_512M 1
214 #define DTH_TRFC_127_5_1G 2
215 #define DTH_TRFC_195_2G 3
216 #define DTH_TRFC_327_5_4G 4
219 #define DTH_TRFC_90_512M 1
220 #define DTH_TRFC_110_5_1G 2
221 #define DTH_TRFC_160_2G 3
222 #define DTH_TRFC_300_4G 4
223 #define DTH_TRFC_UNDEFINED_8G 5
225 #define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */
226 #define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */
227 #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
229 #define DRAM_CONFIG_LOW 0x90
230 #define DCL_InitDram (1<<0)
231 #define DCL_ExitSelfRef (1<<1)
232 #define DCL_PllLockTime_SHIFT 2
233 #define DCL_PllLockTime_MASK 3
234 #define DCL_PllLockTime_15US 0
235 #define DCL_PllLockTime_6US 1
236 #define DCL_DramTerm_SHIFT 4
237 #define DCL_DramTerm_MASK 3
238 #define DCL_DramTerm_No 0
239 #define DCL_DramTerm_75_OH 1
240 #define DCL_DramTerm_150_OH 2
241 #define DCL_DramTerm_50_OH 3
242 #define DCL_DisDqsBar (1<<6) /* only for DDR2 */
243 #define DCL_DramDrvWeak (1<<7) /* only for DDR2 */
244 #define DCL_ParEn (1<<8)
245 #define DCL_SelfRefRateEn (1<<9) /* only for DDR2 */
246 #define DCL_BurstLength32 (1<<10) /* only for DDR3 */
247 #define DCL_Width128 (1<<11)
248 #define DCL_X4Dimm_SHIFT 12
249 #define DCL_X4Dimm_MASK 0xf
250 #define DCL_UnBuffDimm (1<<16)
251 #define DCL_EnPhyDqsRcvEnTr (1<<18)
252 #define DCL_DimmEccEn (1<<19)
253 #define DCL_DynPageCloseEn (1<<20)
254 #define DCL_IdleCycInit_SHIFT 21
255 #define DCL_IdleCycInit_MASK 3
256 #define DCL_IdleCycInit_16CLK 0
257 #define DCL_IdleCycInit_32CLK 1
258 #define DCL_IdleCycInit_64CLK 2
259 #define DCL_IdleCycInit_96CLK 3
260 #define DCL_ForceAutoPchg (1<<23)
262 #define DRAM_CONFIG_HIGH 0x94
263 #define DCH_MemClkFreq_SHIFT 0
264 #define DCH_MemClkFreq_MASK 7
265 #define DCH_MemClkFreq_200MHz 0 /* DDR2 */
266 #define DCH_MemClkFreq_266MHz 1 /* DDR2 */
267 #define DCH_MemClkFreq_333MHz 2 /* DDR2 */
268 #define DCH_MemClkFreq_400MHz 3 /* DDR2 and DDR 3*/
269 #define DCH_MemClkFreq_533MHz 4 /* DDR 3 */
270 #define DCH_MemClkFreq_667MHz 5 /* DDR 3 */
271 #define DCH_MemClkFreq_800MHz 6 /* DDR 3 */
272 #define DCH_MemClkFreqVal (1<<3)
273 #define DCH_Ddr3Mode (1<<8)
274 #define DCH_LegacyBiosMode (1<<9)
275 #define DCH_ZqcsInterval_SHIFT 10
276 #define DCH_ZqcsInterval_MASK 3
277 #define DCH_ZqcsInterval_DIS 0
278 #define DCH_ZqcsInterval_64MS 1
279 #define DCH_ZqcsInterval_128MS 2
280 #define DCH_ZqcsInterval_256MS 3
281 #define DCH_RDqsEn (1<<12) /* only for DDR2 */
282 #define DCH_DisSimulRdWr (1<<13)
283 #define DCH_DisDramInterface (1<<14)
284 #define DCH_PowerDownEn (1<<15)
285 #define DCH_PowerDownMode_SHIFT 16
286 #define DCH_PowerDownMode_MASK 1
287 #define DCH_PowerDownMode_Channel_CKE 0
288 #define DCH_PowerDownMode_ChipSelect_CKE 1
289 #define DCH_FourRankSODimm (1<<17)
290 #define DCH_FourRankRDimm (1<<18)
291 #define DCH_SlowAccessMode (1<<20)
292 #define DCH_BankSwizzleMode (1<<22)
293 #define DCH_DcqBypassMax_SHIFT 24
294 #define DCH_DcqBypassMax_MASK 0xf
295 #define DCH_DcqBypassMax_BASE 0
296 #define DCH_DcqBypassMax_MIN 0
297 #define DCH_DcqBypassMax_MAX 15
298 #define DCH_FourActWindow_SHIFT 28
299 #define DCH_FourActWindow_MASK 0xf
300 #define DCH_FourActWindow_BASE 7 /* DDR3 15 */
301 #define DCH_FourActWindow_MIN 8 /* DDR3 16 */
302 #define DCH_FourActWindow_MAX 20 /* DDR3 30 */
305 // for 0x98 index and 0x9c data for DCT0
306 // for 0x198 index and 0x19c data for DCT1
307 // even at ganged mode, 0x198/0x19c will be used for channnel B
309 #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98
310 #define DCAO_DctOffset_SHIFT 0
311 #define DCAO_DctOffset_MASK 0x3fffffff
312 #define DCAO_DctAccessWrite (1<<30)
313 #define DCAO_DctAccessDone (1<<31)
315 #define DRAM_CTRL_ADDI_DATA_PORT 0x9c
317 #define DRAM_OUTPUT_DRV_COMP_CTRL 0x00
318 #define DODCC_CkeDrvStren_SHIFT 0
319 #define DODCC_CkeDrvStren_MASK 3
320 #define DODCC_CkeDrvStren_1_0X 0
321 #define DODCC_CkeDrvStren_1_25X 1
322 #define DODCC_CkeDrvStren_1_5X 2
323 #define DODCC_CkeDrvStren_2_0X 3
324 #define DODCC_CsOdtDrvStren_SHIFT 4
325 #define DODCC_CsOdtDrvStren_MASK 3
326 #define DODCC_CsOdtDrvStren_1_0X 0
327 #define DODCC_CsOdtDrvStren_1_25X 1
328 #define DODCC_CsOdtDrvStren_1_5X 2
329 #define DODCC_CsOdtDrvStren_2_0X 3
330 #define DODCC_AddrCmdDrvStren_SHIFT 8
331 #define DODCC_AddrCmdDrvStren_MASK 3
332 #define DODCC_AddrCmdDrvStren_1_0X 0
333 #define DODCC_AddrCmdDrvStren_1_25X 1
334 #define DODCC_AddrCmdDrvStren_1_5X 2
335 #define DODCC_AddrCmdDrvStren_2_0X 3
336 #define DODCC_ClkDrvStren_SHIFT 12
337 #define DODCC_ClkDrvStren_MASK 3
338 #define DODCC_ClkDrvStren_0_75X 0
339 #define DODCC_ClkDrvStren_1_0X 1
340 #define DODCC_ClkDrvStren_1_25X 2
341 #define DODCC_ClkDrvStren_1_5X 3
342 #define DODCC_DataDrvStren_SHIFT 16
343 #define DODCC_DataDrvStren_MASK 3
344 #define DODCC_DataDrvStren_0_75X 0
345 #define DODCC_DataDrvStren_1_0X 1
346 #define DODCC_DataDrvStren_1_25X 2
347 #define DODCC_DataDrvStren_1_5X 3
348 #define DODCC_DqsDrvStren_SHIFT 20
349 #define DODCC_DqsDrvStren_MASK 3
350 #define DODCC_DqsDrvStren_0_75X 0
351 #define DODCC_DqsDrvStren_1_0X 1
352 #define DODCC_DqsDrvStren_1_25X 2
353 #define DODCC_DqsDrvStren_1_5X 3
354 #define DODCC_ProcOdt_SHIFT 28
355 #define DODCC_ProcOdt_MASK 3
356 #define DODCC_ProcOdt_300_OHMS 0
357 #define DODCC_ProcOdt_150_OHMS 1
358 #define DODCC_ProcOdt_75_OHMS 2
361 #define DODCC_ProcOdt_240_OHMS 0
362 #define DODCC_ProcOdt_120_OHMS 1
363 #define DODCC_ProcOdt_60_OHMS 2
367 for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs
368 for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0
369 F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1
370 So Socket F with Four Logical DIMM will only support DDR2 800 ?
372 /* there are index +100 ===> for DIMM1
373 that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
376 #define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01
377 #define DWDTC_WrDatFineDlyByte0_SHIFT 0
378 #define DWDTC_WrDatFineDlyByte_MASK 0x1f
379 #define DWDTC_WrDatFineDlyByte_BASE 0
380 #define DWDTC_WrDatFineDlyByte_MIN 0
381 #define DWDTC_WrDatFineDlyByte_MAX 31 // 1/64 MEMCLK
382 #define DWDTC_WrDatGrossDlyByte0_SHIFT 5
383 #define DWDTC_WrDatGrossDlyByte_MASK 0x3
384 #define DWDTC_WrDatGrossDlyByte_NO_DELAY 0
385 #define DWDTC_WrDatGrossDlyByte_0_5_ 1
386 #define DWDTC_WrDatGrossDlyByte_1 2
387 #define DWDTC_WrDatFineDlyByte1_SHIFT 8
388 #define DWDTC_WrDatGrossDlyByte1_SHIFT 13
389 #define DWDTC_WrDatFineDlyByte2_SHIFT 16
390 #define DWDTC_WrDatGrossDlyByte2_SHIFT 21
391 #define DWDTC_WrDatFineDlyByte3_SHIFT 24
392 #define DWDTC_WrDatGrossDlyByte3_SHIFT 29
394 #define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02
395 #define DWDTC_WrDatFineDlyByte4_SHIFT 0
396 #define DWDTC_WrDatGrossDlyByte4_SHIFT 5
397 #define DWDTC_WrDatFineDlyByte5_SHIFT 8
398 #define DWDTC_WrDatGrossDlyByte5_SHIFT 13
399 #define DWDTC_WrDatFineDlyByte6_SHIFT 16
400 #define DWDTC_WrDatGrossDlyByte6_SHIFT 21
401 #define DWDTC_WrDatFineDlyByte7_SHIFT 24
402 #define DWDTC_WrDatGrossDlyByte7_SHIFT 29
404 #define DRAM_WRITE_ECC_TIMING_CTRL 0x03
405 #define DWETC_WrChkFinDly_SHIFT 0
406 #define DWETC_WrChkGrossDly_SHIFT 5
408 #define DRAM_ADDR_CMD_TIMING_CTRL 0x04
409 #define DACTC_CkeFineDelay_SHIFT 0
410 #define DACTC_CkeFineDelay_MASK 0x1f
411 #define DACTC_CkeFineDelay_BASE 0
412 #define DACTC_CkeFineDelay_MIN 0
413 #define DACTC_CkeFineDelay_MAX 31
414 #define DACTC_CkeSetup (1<<5)
415 #define DACTC_CsOdtFineDelay_SHIFT 8
416 #define DACTC_CsOdtFineDelay_MASK 0x1f
417 #define DACTC_CsOdtFineDelay_BASE 0
418 #define DACTC_CsOdtFineDelay_MIN 0
419 #define DACTC_CsOdtFineDelay_MAX 31
420 #define DACTC_CsOdtSetup (1<<13)
421 #define DACTC_AddrCmdFineDelay_SHIFT 16
422 #define DACTC_AddrCmdFineDelay_MASK 0x1f
423 #define DACTC_AddrCmdFineDelay_BASE 0
424 #define DACTC_AddrCmdFineDelay_MIN 0
425 #define DACTC_AddrCmdFineDelay_MAX 31
426 #define DACTC_AddrCmdSetup (1<<21)
428 #define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05
429 #define DRDTC_RdDqsTimeByte0_SHIFT 0
430 #define DRDTC_RdDqsTimeByte_MASK 0x3f
431 #define DRDTC_RdDqsTimeByte_BASE 0
432 #define DRDTC_RdDqsTimeByte_MIN 0
433 #define DRDTC_RdDqsTimeByte_MAX 63 // 1/128 MEMCLK
434 #define DRDTC_RdDqsTimeByte1_SHIFT 8
435 #define DRDTC_RdDqsTimeByte2_SHIFT 16
436 #define DRDTC_RdDqsTimeByte3_SHIFT 24
438 #define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06
439 #define DRDTC_RdDqsTimeByte4_SHIFT 0
440 #define DRDTC_RdDqsTimeByte5_SHIFT 8
441 #define DRDTC_RdDqsTimeByte6_SHIFT 16
442 #define DRDTC_RdDqsTimeByte7_SHIFT 24
444 #define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07
445 #define DRDETC_RdDqsTimeCheck_SHIFT 0
447 #define DRAM_PHY_CTRL 0x08
448 #define DPC_WrtLvTrEn (1<<0)
449 #define DPC_WrtLvTrMode (1<<1)
450 #define DPC_TrNibbleSel (1<<2)
451 #define DPC_TrDimmSel_SHIFT 4
452 #define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */
453 #define DPC_WrLvOdt_SHIFT 8
454 #define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/
455 #define DPC_WrLvODtEn (1<<12)
456 #define DPC_DqsRcvTrEn (1<<13)
457 #define DPC_DisAutoComp (1<<30)
458 #define DPC_AsyncCompUpdate (1<<31)
460 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_0 0x10 //DIMM0 Channel A
461 #define DDRETC_DqsRcvEnFineDelayByte0_SHIFT 0
462 #define DDRETC_DqsRcvEnFineDelayByte0_MASK 0x1f
463 #define DDRETC_DqsRcvEnGrossDelayByte0_SHIFT 5
464 #define DDRETC_DqsRcvEnGrossDelayByte0_MASK 0x3
465 #define DDRETC_DqsRcvEnFineDelayByte1_SHIFT 8
466 #define DDRETC_DqsRcvEnGrossDelayByte1_SHIFT 13
467 #define DDRETC_DqsRcvEnFineDelayByte2_SHIFT 16
468 #define DDRETC_DqsRcvEnGrossDelayByte2_SHIFT 21
469 #define DDRETC_DqsRcvEnFineDelayByte3_SHIFT 24
470 #define DDRETC_DqsRcvEnGrossDelayByte3_SHIFT 29
472 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_1 0x11 //DIMM0 Channel A
473 #define DDRETC_DqsRcvEnFineDelayByte4_SHIFT 0
474 #define DDRETC_DqsRcvEnGrossDelayByte4_SHIFT 5
475 #define DDRETC_DqsRcvEnFineDelayByte5_SHIFT 8
476 #define DDRETC_DqsRcvEnGrossDelayByte5_SHIFT 13
477 #define DDRETC_DqsRcvEnFineDelayByte6_SHIFT 16
478 #define DDRETC_DqsRcvEnGrossDelayByte6_SHIFT 21
479 #define DDRETC_DqsRcvEnFineDelayByte7_SHIFT 24
480 #define DDRETC_DqsRcvEnGrossDelayByte7_SHIFT 29
482 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_0 0x12
483 #define DDRETCE_WrChkFineDlyByte0_SHIFT 0
484 #define DDRETCE_WrChkGrossDlyByte0_SHIFT 5
486 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_2 0x20 //DIMM0 channel B
487 #define DDRETC_DqsRcvEnFineDelayByte8_SHIFT 0
488 #define DDRETC_DqsRcvEnGrossDelayByte8_SHIFT 5
489 #define DDRETC_DqsRcvEnFineDelayByte9_SHIFT 8
490 #define DDRETC_DqsRcvEnGrossDelayByte9_SHIFT 13
491 #define DDRETC_DqsRcvEnFineDelayByte10_SHIFT 16
492 #define DDRETC_DqsRcvEnGrossDelayByte10_SHIFT 21
493 #define DDRETC_DqsRcvEnFineDelayByte11_SHIFT 24
494 #define DDRETC_DqsRcvEnGrossDelayByte11_SHIFT 29
496 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_3 0x21 // DIMM0 Channel B
497 #define DDRETC_DqsRcvEnFineDelayByte12_SHIFT 0
498 #define DDRETC_DqsRcvEnGrossDelayByte12_SHIFT 5
499 #define DDRETC_DqsRcvEnFineDelayByte13_SHIFT 8
500 #define DDRETC_DqsRcvEnGrossDelayByte13_SHIFT 13
501 #define DDRETC_DqsRcvEnFineDelayByte14_SHIFT 16
502 #define DDRETC_DqsRcvEnGrossDelayByte14_SHIFT 21
503 #define DDRETC_DqsRcvEnFineDelayByte15_SHIFT 24
504 #define DDRETC_DqsRcvEnGrossDelayByte15_SHIFT 29
506 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_1 0x22
507 #define DDRETCE_WrChkFineDlyByte1_SHIFT 0
508 #define DDRETCE_WrChkGrossDlyByte1_SHIFT 5
510 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_0 0x13 //DIMM1
511 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_1 0x14
512 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_0 0x15
513 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_2 0x23
514 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_3 0x24
515 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_1 0x25
517 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_0 0x16 // DIMM2
518 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_1 0x17
519 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_0 0x18
520 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_2 0x26
521 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_3 0x27
522 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_1 0x28
524 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_0 0x19 // DIMM3
525 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_1 0x1a
526 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_0 0x1b
527 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_2 0x29
528 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_3 0x2a
529 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_1 0x2b
531 /* 04.06.2006 19:12 */
535 #define DRAM_DQS_WRITE_TIME_CTRL_0_0 0x30 //DIMM0 Channel A
536 #define DDWTC_WrDqsFineDlyByte0_SHIFT 0
537 #define DDWTC_WrDqsFineDlyByte0_MASK 0x1f
538 #define DDWTC_WrDqsGrossDlyByte0_SHIFT 5
539 #define DDWTC_WrDqsGrossDlyByte0_MASK 0x3
540 #define DDWTC_WrDqsFineDlyByte1_SHIFT 8
541 #define DDWTC_WrDqsGrossDlyByte1_SHIFT 13
542 #define DDWTC_WrDqsFineDlyByte2_SHIFT 16
543 #define DDWTC_WrDqsGrossDlyByte2_SHIFT 21
544 #define DDWTC_WrDqsFineDlyByte3_SHIFT 24
545 #define DDWTC_WrDqsGrossDlyByte3_SHIFT 29
547 #define DRAM_DQS_WRTIE_TIME_CTRL_0_1 0x31 //DIMM0 Channel A
548 #define DDWTC_WrDqsFineDlyByte4_SHIFT 0
549 #define DDWTC_WrDqsGrossDlyByte4_SHIFT 5
550 #define DDWTC_WrDqsFineDlyByte5_SHIFT 8
551 #define DDWTC_WrDqsGrossDlyByte5_SHIFT 13
552 #define DDWTC_WrDqsFineDlyByte6_SHIFT 16
553 #define DDWTC_WrDqsGrossDlyByte6_SHIFT 21
554 #define DDWTC_WrDqsFineDlyByte7_SHIFT 24
555 #define DDWTC_WrDqsGrossDlyByte7_SHIFT 29
557 #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_0 0x32
558 #define DDWTCE_WrDqsChkFineDlyByte0_SHIFT 0
559 #define DDWTCE_WrDqsChkGrossDlyByte0_SHIFT 5
561 #define DRAM_DQS_WRITE_TIME_CTRL_0_2 0x40 //DIMM0 Channel B
562 #define DDWTC_WrDqsFineDlyByte8_SHIFT 0
563 #define DDWTC_WrDqsGrossDlyByte8_SHIFT 5
564 #define DDWTC_WrDqsFineDlyByte9_SHIFT 8
565 #define DDWTC_WrDqsGrossDlyByte9_SHIFT 13
566 #define DDWTC_WrDqsFineDlyByte10_SHIFT 16
567 #define DDWTC_WrDqsGrossDlyByte10_SHIFT 21
568 #define DDWTC_WrDqsFineDlyByte11_SHIFT 24
569 #define DDWTC_WrDqsGrossDlyByte11_SHIFT 29
571 #define DRAM_DQS_WRTIE_TIME_CTRL_0_3 0x41 //DIMM0 Channel B
572 #define DDWTC_WrDqsFineDlyByte12_SHIFT 0
573 #define DDWTC_WrDqsGrossDlyByte12_SHIFT 5
574 #define DDWTC_WrDqsFineDlyByte13_SHIFT 8
575 #define DDWTC_WrDqsGrossDlyByte13_SHIFT 13
576 #define DDWTC_WrDqsFineDlyByte14_SHIFT 16
577 #define DDWTC_WrDqsGrossDlyByte14_SHIFT 21
578 #define DDWTC_WrDqsFineDlyByte15_SHIFT 24
579 #define DDWTC_WrDqsGrossDlyByte15_SHIFT 29
581 #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_1 0x42
582 #define DDWTCE_WrDqsChkFineDlyByte1_SHIFT 0
583 #define DDWTCE_WrDqsChkGrossDlyByte1_SHIFT 5
585 #define DRAM_DQS_WRITE_TIME_CTRL_1_0 0x33 //DIMM1 Channel A
586 #define DRAM_DQS_WRTIE_TIME_CTRL_1_1 0x34 //DIMM1 Channel A
587 #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_1_0 0x35
588 #define DRAM_DQS_WRITE_TIME_CTRL_1_2 0x43 //DIMM1 Channel B
589 #define DRAM_DQS_WRTIE_TIME_CTRL_1_3 0x44 //DIMM1 Channel B
590 #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_1_1 0x45
593 #define DRAM_PHASE_RECOVERY_CTRL_0 0x50
594 #define DPRC_PhRecFineDlyByte0_SHIFT 0
595 #define DDWTC_PhRecFineDlyByte0_MASK 0x1f
596 #define DDWTC_PhRecGrossDlyByte0_SHIFT 5
597 #define DDWTC_PhRecGrossDlyByte0_MASK 0x3
598 #define DDWTC_PhRecFineDlyByte1_SHIFT 8
599 #define DDWTC_PhRecGrossDlyByte1_SHIFT 13
600 #define DDWTC_PhRecFineDlyByte2_SHIFT 16
601 #define DDWTC_PhRecGrossDlyByte2_SHIFT 21
602 #define DDWTC_PhRecFineDlyByte3_SHIFT 24
603 #define DDWTC_PhRecGrossDlyByte3_SHIFT 29
605 #define DRAM_PHASE_RECOVERY_CTRL_1 0x51
606 #define DPRC_PhRecFineDlyByte4_SHIFT 0
607 #define DDWTC_PhRecGrossDlyByte4_SHIFT 5
608 #define DDWTC_PhRecFineDlyByte5_SHIFT 8
609 #define DDWTC_PhRecGrossDlyByte5_SHIFT 13
610 #define DDWTC_PhRecFineDlyByte6_SHIFT 16
611 #define DDWTC_PhRecGrossDlyByte6_SHIFT 21
612 #define DDWTC_PhRecFineDlyByte7_SHIFT 24
613 #define DDWTC_PhRecGrossDlyByte7_SHIFT 29
615 #define DRAM_ECC_PHASE_RECOVERY_CTRL 0x52
616 #define DEPRC_PhRecEccDlyByte0_SHIFT 0
617 #define DEPRC_PhRecEccGrossDlyByte0_SHIFT 5
619 #define DRAM_WRITE_LEVEL_ERROR 0x53 /* read only */
620 #define DWLE_WrLvErr_SHIFT 0
621 #define DWLE_WrLvErr_MASK 0xff
623 #define DRAM_CTRL_MISC 0xa0
624 #define DCM_MemCleared (1<<0) /* RD == F2x110 [MemCleared] */
625 #define DCM_DramEnabled (1<<9) /* RD == F2x110 [DramEnabled] */
627 #define NB_TIME_STAMP_COUNT_LOW 0xb0
628 #define TscLow_SHIFT 0
629 #define TscLow_MASK 0xffffffff
631 #define NB_TIME_STAMP_COUNT_HIGH 0xb4
632 #define TscHigh_SHIFT 0
633 #define TscHigh_Mask 0xff
635 #define DCT_DEBUG_CTRL 0xf0 /* 0xf0 for DCT0, 0x1f0 is for DCT1*/
636 #define DDC_DllAdjust_SHIFT 0
637 #define DDC_DllAdjust_MASK 0xff
638 #define DDC_DllSlower (1<<8)
639 #define DDC_DllFaster (1<<9)
640 #define DDC_WrtDqsAdjust_SHIFT 16
641 #define DDC_WrtDqsAdjust_MASK 0x7
642 #define DDC_WrtDqsAdjustEn (1<<19)
644 #define DRAM_CTRL_SEL_LOW 0x110
645 #define DCSL_DctSelHiRngEn (1<<0)
646 #define DCSL_DctSelHi (1<<1)
647 #define DCSL_DctSelIntLvEn (1<<2)
648 #define DCSL_MemClrInit (1<<3) /* WR only */
649 #define DCSL_DctGangEn (1<<4)
650 #define DCSL_DctDataIntLv (1<<5)
651 #define DCSL_DctSelIntLvAddr_SHIFT
652 #define DCSL_DctSelIntLvAddr_MASK 3
653 #define DCSL_DramEnable (1<<8) /* RD only */
654 #define DCSL_MemClrBusy (1<<9) /* RD only */
655 #define DCSL_MemCleared (1<<10) /* RD only */
656 #define DCSL_DctSelBaseAddr_47_27_SHIFT 11
657 #define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff
659 #define DRAM_CTRL_SEL_HIGH 0x114
660 #define DCSH_DctSelBaseOffset_47_26_SHIFT 10
661 #define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff
663 #define MEM_CTRL_CONF_LOW 0x118
664 #define MCCL_MctPriCpuRd (1<<0)
665 #define MCCL_MctPriCpuWr (1<<1)
666 #define MCCL_MctPriIsocRd_SHIFT 4
667 #define MCCL_MctPriIsoc_MASK 0x3
668 #define MCCL_MctPriIsocWr_SHIFT 6
669 #define MCCL_MctPriIsocWe_MASK 0x3
670 #define MCCL_MctPriDefault_SHIFT 8
671 #define MCCL_MctPriDefault_MASK 0x3
672 #define MCCL_MctPriWr_SHIFT 10
673 #define MCCL_MctPriWr_MASK 0x3
674 #define MCCL_MctPriIsoc_SHIFT 12
675 #define MCCL_MctPriIsoc_MASK 0x3
676 #define MCCL_MctPriTrace_SHIFT 14
677 #define MCCL_MctPriTrace_MASK 0x3
678 #define MCCL_MctPriScrub_SHIFT 16
679 #define MCCL_MctPriScrub_MASK 0x3
680 #define MCCL_McqMedPriByPassMax_SHIFT 20
681 #define MCCL_McqMedPriByPassMax_MASK 0x7
682 #define MCCL_McqHiPriByPassMax_SHIFT 24
683 #define MCCL_McqHiPriByPassMax_MASK 0x7
684 #define MCCL_MctVarPriCntLmt_SHIFT 28
685 #define MCCL_MctVarPriCntLmt_MASK 0x7
687 #define MEM_CTRL_CONF_HIGH 0x11c
688 #define MCCH_DctWrLimit_SHIFT 0
689 #define MCCH_DctWrLimit_MASK 0x3
690 #define MCCH_MctWrLimit_SHIFT 2
691 #define MCCH_MctWrLimit_MASK 0x1f
692 #define MCCH_MctPrefReqLimit_SHIFT 7
693 #define MCCH_MctPrefReqLimit_MASK 0x1f
694 #define MCCH_PrefCpuDis (1<<12)
695 #define MCCH_PrefIoDis (1<<13)
696 #define MCCH_PrefIoFixStrideEn (1<<14)
697 #define MCCH_PrefFixStrideEn (1<<15)
698 #define MCCH_PrefFixDist_SHIFT 16
699 #define MCCH_PrefFixDist_MASK 0x3
700 #define MCCH_PrefConfSat_SHIFT 18
701 #define MCCH_PrefConfSat_MASK 0x3
702 #define MCCH_PrefOneConf_SHIFT 20
703 #define MCCH_PrefOneConf_MASK 0x3
704 #define MCCH_PrefTwoConf_SHIFT 22
705 #define MCCH_PrefTwoConf_MASK 0x7
706 #define MCCH_PrefThreeConf_SHIFT 25
707 #define MCCH_prefThreeConf_MASK 0x7
708 #define MCCH_PrefDramTrainMode (1<<28)
709 #define MCCH_FlushWrOnStpGnt (1<<29)
710 #define MCCH_FlushWr (1<<30)
711 #define MCCH_MctScrubEn (1<<31)
715 #define MCA_NB_CONTROL 0x40
716 #define MNCT_CorrEccEn (1<<0)
717 #define MNCT_UnCorrEccEn (1<<1)
718 #define MNCT_CrcErr0En (1<<2) /* Link 0 */
719 #define MNCT_CrcErr1En (1<<3)
720 #define MNCT_CrcErr2En (1<<4)
721 #define MBCT_SyncPkt0En (1<<5) /* Link 0 */
722 #define MBCT_SyncPkt1En (1<<6)
723 #define MBCT_SyncPkt2En (1<<7)
724 #define MBCT_MstrAbrtEn (1<<8)
725 #define MBCT_TgtAbrtEn (1<<9)
726 #define MBCT_GartTblEkEn (1<<10)
727 #define MBCT_AtomicRMWEn (1<<11)
728 #define MBCT_WdogTmrRptEn (1<<12)
729 #define MBCT_DevErrEn (1<<13)
730 #define MBCT_L3ArrayCorEn (1<<14)
731 #define MBCT_L3ArrayUncEn (1<<15)
732 #define MBCT_HtProtEn (1<<16)
733 #define MBCT_HtDataEn (1<<17)
734 #define MBCT_DramParEn (1<<18)
735 #define MBCT_RtryHt0En (1<<19) /* Link 0 */
736 #define MBCT_RtryHt1En (1<<20)
737 #define MBCT_RtryHt2En (1<<21)
738 #define MBCT_RtryHt3En (1<<22)
739 #define MBCT_CrcErr3En (1<<23) /* Link 3*/
740 #define MBCT_SyncPkt3En (1<<24) /* Link 4 */
741 #define MBCT_McaUsPwDatErrEn (1<<25)
742 #define MBCT_NbArrayParEn (1<<26)
743 #define MBCT_TblWlkDatErrEn (1<<27)
744 #define MBCT_FbDimmCorErrEn (1<<28)
745 #define MBCT_FbDimmUnCorErrEn (1<<29)
749 #define MCA_NB_CONFIG 0x44
750 #define MNC_CpuRdDatErrEn (1<<1)
751 #define MNC_SyncOnUcEccEn (1<<2)
752 #define MNC_SynvPktGenDis (1<<3)
753 #define MNC_SyncPktPropDis (1<<4)
754 #define MNC_IoMstAbortDis (1<<5)
755 #define MNC_CpuErrDis (1<<6)
756 #define MNC_IoErrDis (1<<7)
757 #define MNC_WdogTmrDis (1<<8)
758 #define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */
759 #define MNC_WdogTmrCntSel_2_0_MASK 0x3
760 #define MNC_WdogTmrBaseSel_SHIFT 12
761 #define MNC_WdogTmrBaseSel_MASK 0x3
762 #define MNC_LdtLinkSel_SHIFT 14
763 #define MNC_LdtLinkSel_MASK 0x3
764 #define MNC_GenCrcErrByte0 (1<<16)
765 #define MNC_GenCrcErrByte1 (1<<17)
766 #define MNC_SubLinkSel_SHIFT 18
767 #define MNC_SubLinkSel_MASK 0x3
768 #define MNC_SyncOnWdogEn (1<<20)
769 #define MNC_SyncOnAnyErrEn (1<<21)
770 #define MNC_DramEccEn (1<<22)
771 #define MNC_ChipKillEccEn (1<<23)
772 #define MNC_IoRdDatErrEn (1<<24)
773 #define MNC_DisPciCfgCpuErrRsp (1<<25)
774 #define MNC_CorrMcaExcEn (1<<26)
775 #define MNC_NbMcaToMstCpuEn (1<<27)
776 #define MNC_DisTgtAbtCpuErrRsp (1<<28)
777 #define MNC_DisMstAbtCpuErrRsp (1<<29)
778 #define MNC_SyncOnDramAdrParErrEn (1<<30)
779 #define MNC_NbMcaLogEn (1<<31)
781 #define MCA_NB_STATUS_LOW 0x48
782 #define MNSL_ErrorCode_SHIFT 0
783 #define MNSL_ErrorCode_MASK 0xffff
784 #define MNSL_ErrorCodeExt_SHIFT 16
785 #define MNSL_ErrorCodeExt_MASK 0x1f
786 #define MNSL_Syndrome_15_8_SHIFT 24
787 #define MNSL_Syndrome_15_8_MASK 0xff
789 #define MCA_NB_STATUS_HIGH 0x4c
790 #define MNSH_ErrCPU_SHIFT 0
791 #define MNSH_ErrCPU_MASK 0xf
792 #define MNSH_LDTLink_SHIFT 4
793 #define MNSH_LDTLink_MASK 0xf
794 #define MNSH_ErrScrub (1<<8)
795 #define MNSH_SubLink (1<<9)
796 #define MNSH_McaStatusSubCache_SHIFT 10
797 #define MNSH_McaStatusSubCache_MASK 0x3
798 #define MNSH_Deffered (1<<12)
799 #define MNSH_UnCorrECC (1<<13)
800 #define MNSH_CorrECC (1<<14)
801 #define MNSH_Syndrome_7_0_SHIFT 15
802 #define MNSH_Syndrome_7_0_MASK 0xff
803 #define MNSH_PCC (1<<25)
804 #define MNSH_ErrAddrVal (1<<26)
805 #define MNSH_ErrMiscVal (1<<27)
806 #define MNSH_ErrEn (1<<28)
807 #define MNSH_ErrUnCorr (1<<29)
808 #define MNSH_ErrOver (1<<30)
809 #define MNSH_ErrValid (1<<31)
811 #define MCA_NB_ADDR_LOW 0x50
812 #define MNAL_ErrAddr_31_1_SHIFT 1
813 #define MNAL_ErrAddr_31_1_MASK 0x7fffffff
815 #define MCA_NB_ADDR_HIGH 0x54
816 #define MNAL_ErrAddr_47_32_SHIFT 0
817 #define MNAL_ErrAddr_47_32_MASK 0xffff
819 #define DRAM_SCRUB_RATE_CTRL 0x58
823 #define SCRUB_160ns 3
824 #define SCRUB_320ns 4
825 #define SCRUB_640ns 5
826 #define SCRUB_1_28us 6
827 #define SCRUB_2_56us 7
828 #define SCRUB_5_12us 8
829 #define SCRUB_10_2us 9
830 #define SCRUB_20_5us 0xa
831 #define SCRUB_41_0us 0xb
832 #define SCRUB_81_9us 0xc
833 #define SCRUB_163_8us 0xd
834 #define SCRUB_327_7us 0xe
835 #define SCRUB_655_4us 0xf
836 #define SCRUB_1_31ms 0x10
837 #define SCRUB_2_62ms 0x11
838 #define SCRUB_5_24ms 0x12
839 #define SCRUB_10_49ms 0x13
840 #define SCRUB_20_97ms 0x14
841 #define SCRUB_42ms 0x15
842 #define SCRUB_84ms 0x16
843 #define DSRC_DramScrub_SHFIT 0
844 #define DSRC_DramScrub_MASK 0x1f
845 #define DSRC_L2Scrub_SHIFT 8
846 #define DSRC_L2Scrub_MASK 0x1f
847 #define DSRC_DcacheScrub_SHIFT 16
848 #define DSRC_DcacheScrub_MASK 0x1f
849 #define DSRC_L3Scrub_SHIFT 24
850 #define DSRC_L3Scrub_MASK 0x1f
852 #define DRAM_SCRUB_ADDR_LOW 0x5C
853 #define DSAL_ScrubReDirEn (1<<0)
854 #define DSAL_ScrubAddrLo_SHIFT 6
855 #define DSAL_ScrubAddrLo_MASK 0x3ffffff
857 #define DRAM_SCRUB_ADDR_HIGH 0x60
858 #define DSAH_ScrubAddrHi_SHIFT 0
859 #define DSAH_ScrubAddrHi_MASK 0xffff
861 #define HW_THERMAL_CTRL 0x64
863 #define SW_THERMAL_CTRL 0x68
865 #define DATA_BUF_CNT 0x6c
867 #define SRI_XBAR_CMD_BUF_CNT 0x70
869 #define XBAR_SRI_CMD_BUF_CNT 0x74
871 #define MCT_XBAR_CMD_BUF_CNT 0x78
873 #define ACPI_PWR_STATE_CTRL 0x80 /* till 0x84 */
875 #define NB_CONFIG_LOW 0x88
876 #define NB_CONFIG_HIGH 0x8c
878 #define GART_APERTURE_CTRL 0x90
880 #define GART_APERTURE_BASE 0x94
882 #define GART_TBL_BASE 0x98
884 #define GART_CACHE_CTRL 0x9c
886 #define PWR_CTRL_MISC 0xa0
888 #define RPT_TEMP_CTRL 0xa4
890 #define ON_LINE_SPARE_CTRL 0xb0
892 #define SBI_P_STATE_LIMIT 0xc4
894 #define CLK_PWR_TIMING_CTRL0 0xd4
895 #define CLK_PWR_TIMING_CTRL1 0xd8
896 #define CLK_PWR_TIMING_CTRL2 0xdc
898 #define THERMTRIP_STATUS 0xE4
901 #define NORTHBRIDGE_CAP 0xE8
902 #define NBCAP_TwoChanDRAMcap (1 << 0)
903 #define NBCAP_DualNodeMPcap (1 << 1)
904 #define NBCAP_EightNodeMPcap (1 << 2)
905 #define NBCAP_ECCcap (1 << 3)
906 #define NBCAP_ChipkillECCcap (1 << 4)
907 #define NBCAP_DdrMaxRate_SHIFT 5
908 #define NBCAP_DdrMaxRate_MASK 7
909 #define NBCAP_DdrMaxRate_400 7
910 #define NBCAP_DdrMaxRate_533 6
911 #define NBCAP_DdrMaxRate_667 5
912 #define NBCAP_DdrMaxRate_800 4
913 #define NBCAP_DdrMaxRate_1067 3
914 #define NBCAP_DdrMaxRate_1333 2
915 #define NBCAP_DdrMaxRate_1600 1
916 #define NBCAP_DdrMaxRate_3_2G 6
917 #define NBCAP_DdrMaxRate_4_0G 5
918 #define NBCAP_DdrMaxRate_4_8G 4
919 #define NBCAP_DdrMaxRate_6_4G 3
920 #define NBCAP_DdrMaxRate_8_0G 2
921 #define NBCAP_DdrMaxRate_9_6G 1
922 #define NBCAP_Mem_ctrl_cap (1 << 8)
923 #define MBCAP_SVMCap (1<<9)
924 #define NBCAP_HtcCap (1<<10)
925 #define NBCAP_CmpCap_SHIFT 12
926 #define NBCAP_CmpCap_MASK 3
927 #define NBCAP_MpCap_SHIFT 16
928 #define NBCAP_MpCap_MASK 7
929 #define NBCAP_MpCap_1N 7
930 #define NBCAP_MpCap_2N 6
931 #define NBCAP_MpCap_4N 5
932 #define NBCAP_MpCap_8N 4
933 #define NBCAP_MpCap_32N 0
934 #define NBCAP_UnGangEn_SHIFT 20
935 #define NBCAP_UnGangEn_MASK 0xf
936 #define NBCAP_L3Cap (1<<25)
937 #define NBCAP_HtAcCap (1<<26)
939 /* 04/04/2006 18:00 */
941 #define EXT_NB_MCA_CTRL 0x180
943 #define NB_EXT_CONF 0x188
944 #define DOWNCORE_CTRL 0x190
945 #define DWNCC_DisCore_SHIFT 0
946 #define DWNCC_DisCore_MASK 0xf
948 /* Function 5 for FBDIMM */
949 #define FBD_DRAM_TIMING_LOW
951 #define LinkConnected (1 << 0)
952 #define InitComplete (1 << 1)
953 #define NonCoherent (1 << 2)
954 #define ConnectionPending (1 << 4)
957 #include "amdfam10_nums.h"
961 #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
963 #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
969 #if CONFIG_AMDMCT == 0
974 u8 per_rank; // it is rows + col + bank_lines + data lines */
977 u8 bank; //1, 2, 3 mean 2, 4, 8
979 } __attribute__((packed));
981 struct mem_info { // pernode
983 struct dimm_size sz[DIMM_SOCKETS*2]; // for ungang support
986 u32 single_rank_mask;
989 // u32 registered_mask;
991 u8 is_registered; //don't support mixing on the same channel or between channel
992 u8 is_ecc; //don't support mixing on the same channel or between channel
994 u8 memclk_set; // we need to use this to retrieve the mem param, all dimms need to work at same freq for one node
995 u8 is_cs_interleaved[2]; //cs
997 } __attribute__((packed));
999 #include "../amdmct/mct/mct_d.h"
1002 struct link_pair_t {
1013 } __attribute__((packed));
1015 struct nodes_info_t {
1016 u32 nodes_in_group; // could be 2, 3, 4, 5, 6, 7, 8
1017 u32 groups_in_plane; // could be 1, 2, 3, 4, 5
1018 u32 planes; // could be 1, 2
1019 u32 up_planes; // down planes will be [up_planes, planes)
1020 } __attribute__((packed));
1022 /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
1023 #if CONFIG_AMDMCT == 0
1025 //#define MEM_CS_COPY 1
1026 #define MEM_CS_COPY NODE_NUMS
1028 #if CONFIG_MEM_TRAIN_SEQ == 0
1029 #define DQS_DELAY_COPY NODE_NUMS
1031 // #define DQS_DELAY_COPY 1
1032 #define DQS_DELAY_COPY NODE_NUMS
1038 int32_t needs_reset;
1040 u8 ln[NODE_NUMS*NODE_NUMS];// [0, 3] link n, [4, 7] will be hop num
1041 u16 ln_tn[NODE_NUMS*8]; // for 0x0zzz: bit [0,7] target node num, bit[8,11] respone link from target num; 0x80ff mean not inited, 0x4yyy mean non coherent and yyy is link pair index
1042 struct nodes_info_t nodes_info;
1045 u8 host_link_freq[NODE_NUMS*8]; // record freq for every link from cpu, 0x0f means don't need to touch it
1046 u16 host_link_freq_cap[NODE_NUMS*8]; //cap
1054 u32 ht_c_conf_bus[HC_NUMS]; // 4-->32
1056 struct link_pair_t link_pair[HC_NUMS*4];// enough? only in_conherent, 32 chain and every chain have 4 HT device
1059 struct mem_controller ctrl[NODE_NUMS];
1062 // sMCTStruct MCTData;
1063 // sDCTStruct *DCTNodeData[NODE_NUMS];
1064 // sDCTStruct DCTNodeData_a[NODE_NUMS];
1065 struct MCTStatStruc MCTstat;
1066 struct DCTStatStruc DCTstatA[NODE_NUMS];
1069 u8 ctrl_present[NODE_NUMS];
1070 struct mem_info meminfo[NODE_NUMS];
1071 u8 mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
1075 //if we are getting tight of global space, may need to squesh following to one copy
1076 u32 mem_base[MEM_CS_COPY][2]; // two dct
1077 u32 cs_base[MEM_CS_COPY][2][8]; //8 cs_idx
1078 u32 hole_startk; // 0 mean hole
1080 u8 dqs_delay_a[DQS_DELAY_COPY*2*4*2*9]; //8 node, channel 2, dimm 4, direction 2 , bytelane *9
1081 u8 dqs_rcvr_dly_a[DQS_DELAY_COPY*2*4*9]; //8 node, channel 2, dimm 4, bytelane *9
1082 u8 dqs_rcvr_dly_a_1[9]; //8 node, channel 2, dimm 4, bytelane *9
1085 } __attribute__((packed));
1087 #if CONFIG_AMDMCT == 0
1090 static void soft_reset(void);
1092 static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
1097 unsigned needs_reset = 0;
1099 if(sysinfo->nodes == 1) return; // in case only one cpu installed
1100 for(i=1; i<sysinfo->nodes; i++) {
1101 /* Skip everything if I don't have any memory on this controller */
1102 if(sysinfo->mem_trained[i]==0x00) continue;
1107 mask_hi |= (1<<(i-32));
1114 if(mask_lo & (1<<i)) {
1115 if(sysinfo->mem_trained[i] != 0x80) {
1120 if(mask_hi & (1<<(i-32))) {
1121 if(sysinfo->mem_trained[i] != 0x80) {
1122 mask_hi &= ~(1<<(i-32));
1127 if((!mask_lo) && (!mask_hi)) break;
1133 for(i=0; i<sysinfo->nodes; i++) {
1135 print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
1137 printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
1139 switch(sysinfo->mem_trained[i]) {
1140 case 0: //don't need train
1143 case 0x81: //recv1: fail
1144 case 0x82: //Pos :fail
1145 case 0x83: //recv2: fail
1152 print_debug("mem trained failed\n");
1155 printk_debug("mem trained failed\n");
1164 #endif /* AMDFAM10_H */