2 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
3 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
4 * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
7 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
8 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
10 * Permission is hereby granted to use or copy this program
11 * for any purpose, provided the above notices are retained on all copies.
12 * Permission to modify the code and to distribute modified code is granted,
13 * provided the above notices are retained, and a notice that the code was
14 * modified is included with the above copyright notice.
16 * Some of the machine specific code was borrowed from our GC distribution.
19 /* The following really assume we have a 486 or better. Unfortunately */
20 /* gcc doesn't define a suitable feature test macro based on command */
22 /* We should perhaps test dynamically. */
24 #include "../all_aligned_atomic_load_store.h"
26 /* Real X86 implementations, except for some old WinChips, appear */
27 /* to enforce ordering between memory operations, EXCEPT that a later */
28 /* read can pass earlier writes, presumably due to the visible */
29 /* presence of store buffers. */
30 /* We ignore both the WinChips, and the fact that the official specs */
31 /* seem to be much weaker (and arguably too weak to be usable). */
33 #include "../ordered_except_wr.h"
35 #include "../test_and_set_t_is_char.h"
37 #include "../standard_ao_double_t.h"
39 #if defined(AO_USE_PENTIUM4_INSTRS)
43 __asm__ __volatile__("mfence" : : : "memory");
46 #define AO_HAVE_nop_full
50 /* We could use the cpuid instruction. But that seems to be slower */
51 /* than the default implementation based on test_and_set_full. Thus */
52 /* we omit that bit of misinformation here. */
56 /* As far as we can tell, the lfence and sfence instructions are not */
57 /* currently needed or useful for cached memory accesses. */
59 /* Really only works for 486 and later */
61 AO_fetch_and_add_full (volatile AO_t *p, AO_t incr)
65 __asm__ __volatile__ ("lock; xaddq %0, %1" :
66 "=r" (result), "=m" (*p) : "0" (incr), "m" (*p)
71 #define AO_HAVE_fetch_and_add_full
73 AO_INLINE unsigned char
74 AO_char_fetch_and_add_full (volatile unsigned char *p, unsigned char incr)
78 __asm__ __volatile__ ("lock; xaddb %0, %1" :
79 "=q" (result), "=m" (*p) : "0" (incr), "m" (*p)
84 #define AO_HAVE_char_fetch_and_add_full
86 AO_INLINE unsigned short
87 AO_short_fetch_and_add_full (volatile unsigned short *p, unsigned short incr)
89 unsigned short result;
91 __asm__ __volatile__ ("lock; xaddw %0, %1" :
92 "=r" (result), "=m" (*p) : "0" (incr), "m" (*p)
97 #define AO_HAVE_short_fetch_and_add_full
99 AO_INLINE unsigned int
100 AO_int_fetch_and_add_full (volatile unsigned int *p, unsigned int incr)
104 __asm__ __volatile__ ("lock; xaddl %0, %1" :
105 "=r" (result), "=m" (*p) : "0" (incr), "m" (*p)
110 #define AO_HAVE_int_fetch_and_add_full
112 /* Really only works for 486 and later */
114 AO_or_full (volatile AO_t *p, AO_t incr)
116 __asm__ __volatile__ ("lock; orq %1, %0" :
117 "=m" (*p) : "r" (incr), "m" (*p) : "memory");
120 #define AO_HAVE_or_full
122 AO_INLINE AO_TS_VAL_t
123 AO_test_and_set_full(volatile AO_TS_t *addr)
125 unsigned char oldval;
126 /* Note: the "xchg" instruction does not need a "lock" prefix */
127 __asm__ __volatile__("xchgb %0, %1"
128 : "=q"(oldval), "=m"(*addr)
129 : "0"(0xff), "m"(*addr) : "memory");
130 return (AO_TS_VAL_t)oldval;
133 #define AO_HAVE_test_and_set_full
135 /* Returns nonzero if the comparison succeeded. */
137 AO_compare_and_swap_full(volatile AO_t *addr,
138 AO_t old, AO_t new_val)
141 __asm__ __volatile__("lock; cmpxchgq %3, %0; setz %1"
142 : "=m"(*addr), "=q"(result)
143 : "m"(*addr), "r" (new_val), "a"(old) : "memory");
147 #define AO_HAVE_compare_and_swap_full
149 #ifdef AO_CMPXCHG16B_AVAILABLE
150 /* NEC LE-IT: older AMD Opterons are missing this instruction.
151 * On these machines SIGILL will be thrown. Define AO_CASDOUBLE_MISSING
152 * to have an emulated (lock based) version available */
153 /* HB: Changed this to not define either by default. There are
154 * enough machines and tool chains around on which cmpxchg16b
155 * doesn't work. And the emulation is unsafe by our usual rules.
156 * Hoewever both are clearly useful in certain cases.
159 AO_compare_double_and_swap_double_full(volatile AO_double_t *addr,
160 AO_t old_val1, AO_t old_val2,
161 AO_t new_val1, AO_t new_val2)
164 __asm__ __volatile__("lock; cmpxchg16b %0; setz %1"
165 : "=m"(*addr), "=q"(result)
170 "b" (new_val2) : "memory");
173 #define AO_HAVE_compare_double_and_swap_double_full
175 /* this one provides spinlock based emulation of CAS implemented in */
176 /* atomic_ops.c. We probably do not want to do this here, since it is */
177 /* not atomic with respect to other kinds of updates of *addr. On the */
178 /* other hand, this may be a useful facility on occasion. */
179 #ifdef AO_WEAK_DOUBLE_CAS_EMULATION
180 int AO_compare_double_and_swap_double_emulation(volatile AO_double_t *addr,
181 AO_t old_val1, AO_t old_val2,
182 AO_t new_val1, AO_t new_val2);
185 AO_compare_double_and_swap_double_full(volatile AO_double_t *addr,
186 AO_t old_val1, AO_t old_val2,
187 AO_t new_val1, AO_t new_val2)
189 return AO_compare_double_and_swap_double_emulation(addr,
193 #define AO_HAVE_compare_double_and_swap_double_full
194 #endif /* AO_WEAK_DOUBLE_CAS_EMULATION */
195 #endif /* AO_CMPXCHG16B_AVAILABLE */