2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Nils Jacobs
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <device/pci_def.h>
25 #include <device/pnp_def.h>
27 #include <console/console.h>
28 #include "lib/ramtest.c"
29 #include "cpu/x86/bist.h"
30 #include "cpu/x86/msr.h"
31 #include <cpu/amd/gx2def.h>
32 #include <cpu/amd/geode_post_code.h>
34 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
35 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
37 static inline int spd_read_byte(unsigned device, unsigned address)
39 return smbus_read_byte(device, address);
42 #include "northbridge/amd/gx2/raminit.h"
44 /* This is needed because ROMCC doesn`t now the ctz bitop */
45 static inline unsigned int ctz(unsigned int n)
49 n = (n ^ (n - 1)) >> 1;
50 for (zeros = 0; n; zeros++)
57 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
59 /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
60 * component Banks (byte 17) * module banks, side (byte 5) *
61 * width in bits (byte 6,7)
62 * = Density per side (byte 31) * number of sides (byte 5) */
63 /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
65 unsigned char module_banks, val;
68 msr = rdmsr(MC_CF07_DATA);
70 /* get module banks (sides) per dimm, SPD byte 5 */
71 module_banks = spd_read_byte(0xA0, 5);
72 if (module_banks < 1 || module_banks > 2)
73 print_err("Module banks per dimm\n");
75 msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
76 msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
78 /* get component banks per module bank, SPD byte 17 */
79 val = spd_read_byte(0xA0, 17);
80 if (val < 2 || val > 4)
81 print_err("Component banks per module bank\n");
83 msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
84 msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
86 dimm_size = spd_read_byte(0xA0, 31);
87 dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
88 dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
89 /* Module Density * Module Banks */
90 dimm_size <<= (0 >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
92 dimm_size = ctz(dimm_size);
94 if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
95 print_err("Only support up to 512MB \n");
98 msr.hi |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
100 /* page size = 2^col address */
101 val = spd_read_byte(0xA0, 4);
103 msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
104 msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
106 print_debug("computed msr.hi ");
107 print_debug_hex32(msr.hi);
111 wrmsr(MC_CF07_DATA, msr);
113 msr = rdmsr(MC_CF8F_DATA);
116 wrmsr(MC_CF8F_DATA, msr);
120 #include "northbridge/amd/gx2/raminit.c"
121 #include "lib/generic_sdram.c"
122 #include "northbridge/amd/gx2/pll_reset.c"
123 #include "cpu/amd/model_gx2/cpureginit.c"
124 #include "cpu/amd/model_gx2/syspreinit.c"
125 #include "cpu/amd/model_lx/msrinit.c"
127 void main(unsigned long bist)
129 static const struct mem_controller memctrl [] = {
130 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
135 cs5536_early_setup();
137 /* disable the power button */
138 outl(0x00, PMS_IO_BASE + 0x40);
140 /* cs5536_disable_internal_uart disable them. Set them up now... */
141 cs5536_setup_onchipuart(1);
146 /* Halt if there was a built in self test failure */
147 report_bist_failure(bist);
152 print_err("done cpuRegInit\n");
154 sdram_initialize(1, memctrl);
155 print_err("ram setup done\n");
159 /* Check all of memory */
160 /*ram_check(0x00000000, 640*1024);*/
161 print_err("ram check done\n");