2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <device/pci_def.h>
24 #include <device/pci_ids.h>
26 #include <device/pnp_def.h>
27 #include <arch/romcc_io.h>
29 #include <console/console.h>
31 #include "northbridge/via/cx700/raminit.h"
32 #include "cpu/x86/bist.h"
35 #include "pc80/udelay_io.c"
36 #include "lib/delay.c"
37 #include "northbridge/via/cx700/cx700_early_smbus.c"
38 #include "lib/debug.c"
40 #include "northbridge/via/cx700/cx700_early_serial.c"
41 #include "northbridge/via/cx700/raminit.c"
43 static void enable_mainboard_devices(void)
47 dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
48 if (dev == PCI_DEV_INVALID) {
49 die("LPC bridge not found!!!\n");
52 pci_write_config8(dev, 0x98, 0x00);
55 pci_write_config8(dev, 0x50, 0x80);
57 // Disable internal KBC Configuration
58 pci_write_config8(dev, 0x51, 0x2d);
59 pci_write_config8(dev, 0x58, 0x42);
60 pci_write_config8(dev, 0x59, 0x80);
61 pci_write_config8(dev, 0x5b, 0x01);
63 // Enable P2P Bridge Header for External PCI BUS.
64 dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0);
65 if (dev == PCI_DEV_INVALID) {
66 die("P2P bridge not found!!!\n");
68 pci_write_config8(dev, 0x4f, 0x41);
70 // Switch SATA to non-RAID mode
71 dev = pci_locate_device(PCI_ID(0x1106, 0x0581), 0);
72 if (dev != PCI_DEV_INVALID) {
73 pci_write_config16(dev, 0xBA, 0x5324);
77 static void enable_shadow_ram(const struct mem_controller *ctrl)
81 pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a);
83 /* 0xf0000-0xfffff - ACPI tables */
84 shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
86 pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
89 void main(unsigned long bist)
91 /* Set statically so it should work with cx700 as well */
92 static const struct mem_controller cx700[] = {
94 .channel0 = {DIMM0, DIMM1},
100 enable_cx700_serial();
104 /* Halt if there was a built in self test failure */
105 report_bist_failure(bist);
107 enable_mainboard_devices();
109 /* Allows access to all northbridge devices */
110 pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
112 sdram_set_registers(cx700);
113 enable_shadow_ram(cx700);