src/mainboard/via/vt8454c/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22 #include <stdint.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <arch/romcc_io.h>
  28 #include <arch/hlt.h>
  29 #include "pc80/serial.c"
  30 #include "console/console.c"
  31 #include "lib/ramtest.c"
  32 #include "northbridge/via/cx700/raminit.h"
  33 #include "cpu/x86/bist.h"
  34
  35 #define DEACTIVATE_CAR 1
  36 #define DEACTIVATE_CAR_FILE "cpu/via/car/cache_as_ram_post.c"
  37 #include "cpu/x86/car/copy_and_run.c"
  38 #include "pc80/udelay_io.c"
  39 #include "lib/delay.c"
  40 #include "northbridge/via/cx700/cx700_early_smbus.c"
  41 #include "lib/debug.c"
  42
  43 #include "northbridge/via/cx700/cx700_early_serial.c"
  44 #include "northbridge/via/cx700/raminit.c"
  45
  46 static void enable_mainboard_devices(void)
  47 {
  48         device_t dev;
  49
  50         dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
  51         if (dev == PCI_DEV_INVALID) {
  52                 die("LPC bridge not found!!!\n");
  53         }
  54         // Disable GP3
  55         pci_write_config8(dev, 0x98, 0x00);
  56
  57         // Disable mc97
  58         pci_write_config8(dev, 0x50, 0x80);
  59
  60         // Disable internal KBC Configuration
  61         pci_write_config8(dev, 0x51, 0x2d);
  62         pci_write_config8(dev, 0x58, 0x42);
  63         pci_write_config8(dev, 0x59, 0x80);
  64         pci_write_config8(dev, 0x5b, 0x01);
  65
  66         // Enable P2P Bridge Header for External PCI BUS.
  67         dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0);
  68         if (dev == PCI_DEV_INVALID) {
  69                 die("P2P bridge not found!!!\n");
  70         }
  71         pci_write_config8(dev, 0x4f, 0x41);
  72
  73         // Switch SATA to non-RAID mode
  74         dev = pci_locate_device(PCI_ID(0x1106, 0x0581), 0);
  75         if (dev != PCI_DEV_INVALID) {
  76                 pci_write_config16(dev, 0xBA, 0x5324);
  77         }
  78 }
  79
  80 static void enable_shadow_ram(const struct mem_controller *ctrl)
  81 {
  82         u8 shadowreg;
  83
  84         pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a);
  85
  86         /* 0xf0000-0xfffff - ACPI tables */
  87         shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
  88         shadowreg |= 0x30;
  89         pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
  90 }
  91
  92 static void main(unsigned long bist)
  93 {
  94         /* Set statically so it should work with cx700 as well */
  95         static const struct mem_controller cx700[] = {
  96                 {
  97                         .channel0 = {0x50, 0x51},
  98                 },
  99         };
 100
 101         enable_smbus();
 102
 103         enable_cx700_serial();
 104         uart_init();
 105         console_init();
 106
 107         /* Halt if there was a built in self test failure */
 108         report_bist_failure(bist);
 109
 110         enable_mainboard_devices();
 111
 112         /* Allows access to all northbridge devices */
 113         pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
 114
 115         sdram_set_registers(cx700);
 116         enable_shadow_ram(cx700);
 117         sdram_enable(cx700);
 118
 119 #ifdef DEACTIVATE_CAR
 120         print_debug("Deactivating CAR");
 121 #include DEACTIVATE_CAR_FILE
 122         print_debug(" - Done.\n");
 123 #endif
 124         copy_and_run(0);
 125 }
 126
 127 void stage1_main(unsigned long bist)
 128 {
 129         main(bist);
 130 }
 131