2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2009 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 uses HAVE_OPTION_TABLE
30 uses USE_FALLBACK_IMAGE
31 uses HAVE_FALLBACK_BOOT
35 uses MAINBOARD_PART_NUMBER
36 uses COREBOOT_EXTRA_VERSION
45 uses ROM_SECTION_OFFSET
48 uses CONFIG_ROM_PAYLOAD
49 uses CONFIG_ROM_PAYLOAD_START
50 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
51 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
68 uses DEFAULT_CONSOLE_LOGLEVEL
69 uses MAXIMUM_CONSOLE_LOGLEVEL
70 uses CONFIG_CONSOLE_SERIAL8250
75 uses CONFIG_UDELAY_TSC
76 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
77 uses CONFIG_PCI_ROM_RUN
78 uses CONFIG_CONSOLE_VGA
79 uses CONFIG_MAX_PCI_BUSES
88 uses CONFIG_USE_PRINTK_IN_CAR
90 ## ROM_SIZE is the size of boot ROM that this board will use.
91 default ROM_SIZE = 256*1024
93 default USE_DCACHE_RAM=1
94 default DCACHE_RAM_BASE=0xffef0000
95 #default DCACHE_RAM_BASE=0xffbf0000
96 #default DCACHE_RAM_BASE=0xfec00000
97 default DCACHE_RAM_SIZE=0x8000
98 default CONFIG_USE_PRINTK_IN_CAR=1
101 ### Leave this to 0; VGA is handled by seperate code.
103 default CONFIG_PCI_ROM_RUN=0
104 default CONFIG_CONSOLE_VGA=0
107 ## Build code for the fallback boot
109 default HAVE_FALLBACK_BOOT=1
112 ## Use TSC for udelay.
114 default CONFIG_UDELAY_TSC=1
115 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
118 ## Build code to reset the motherboard from linuxBIOS
120 default HAVE_HARD_RESET=1
123 ## Build code to export a programmable irq routing table
125 default HAVE_PIRQ_TABLE=1
126 default IRQ_SLOT_COUNT=15
129 ## Build code to export an x86 MP table
130 ## Useful for specifying IRQ routing values
132 default HAVE_MP_TABLE=1
135 ## Build code to load acpi tables
137 default HAVE_ACPI_TABLES=1
140 ## Build code to export a CMOS option table
142 default HAVE_OPTION_TABLE=1
145 ## Build code to fill in tables both in low and high memory
147 default HAVE_LOW_TABLES=1
151 ## Build code to setup a generic IOAPIC
154 default CONFIG_IOAPIC=1
157 ### LinuxBIOS layout values
160 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
161 default ROM_IMAGE_SIZE = 65536
162 default FALLBACK_SIZE = ROM_IMAGE_SIZE
165 ## Use a small 8K stack
167 default STACK_SIZE=0x2000
170 ## Use a small 16K heap
172 default HEAP_SIZE=0x4000
175 ## Only use the option table in a normal image
177 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
178 default USE_OPTION_TABLE = 0
180 default _RAMBASE = 0x00004000
182 default CONFIG_ROM_PAYLOAD = 1
185 ## The default compiler
187 default CROSS_COMPILE=""
188 default CC="$(CROSS_COMPILE)gcc -m32"
192 ## Set this to the max PCI bus number you
193 ## would ever use for PCI config IO.
194 ## Setting this number very high will make
195 ## pci_locate_device take a long time when
196 ## it can't find a device.
198 default CONFIG_MAX_PCI_BUSES = 0x80
201 ## Disable the gdb stub by default
203 default CONFIG_GDB_STUB=0
206 ## The Serial Console
209 # To Enable the Serial Console
210 default CONFIG_CONSOLE_SERIAL8250=1
212 ## Select the serial console baud rate
213 default TTYS0_BAUD=115200
214 #default TTYS0_BAUD=57600
215 #default TTYS0_BAUD=38400
216 #default TTYS0_BAUD=19200
217 #default TTYS0_BAUD=9600
218 #default TTYS0_BAUD=4800
219 #default TTYS0_BAUD=2400
220 #default TTYS0_BAUD=1200
222 # Select the serial console base port
223 default TTYS0_BASE=0x3f8
225 # Select the serial protocol
226 # This defaults to 8 data bits, 1 stop bit, and no parity
227 default TTYS0_LCS=0x3
230 ## Select the coreboot loglevel
232 ## EMERG 1 system is unusable
233 ## ALERT 2 action must be taken immediately
234 ## CRIT 3 critical conditions
235 ## ERR 4 error conditions
236 ## WARNING 5 warning conditions
237 ## NOTICE 6 normal but significant condition
238 ## INFO 7 informational
239 ## DEBUG 8 debug-level messages
240 ## SPEW 9 Way too many details
242 ## Request this level of debugging output
243 default DEFAULT_CONSOLE_LOGLEVEL=5
244 ## At a maximum only compile in this level of debugging
245 default MAXIMUM_CONSOLE_LOGLEVEL=5
250 default CONFIG_CBFS=1