2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2009 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 uses HAVE_OPTION_TABLE
30 uses USE_FALLBACK_IMAGE
31 uses HAVE_FALLBACK_BOOT
35 uses MAINBOARD_PART_NUMBER
36 uses COREBOOT_EXTRA_VERSION
45 uses ROM_SECTION_OFFSET
48 uses CONFIG_ROM_PAYLOAD
49 uses CONFIG_ROM_PAYLOAD_START
50 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
51 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
67 uses DEFAULT_CONSOLE_LOGLEVEL
68 uses MAXIMUM_CONSOLE_LOGLEVEL
69 uses CONFIG_CONSOLE_SERIAL8250
74 uses CONFIG_UDELAY_TSC
75 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
76 uses CONFIG_PCI_ROM_RUN
77 uses CONFIG_CONSOLE_VGA
78 uses CONFIG_MAX_PCI_BUSES
87 uses CONFIG_USE_PRINTK_IN_CAR
89 ## ROM_SIZE is the size of boot ROM that this board will use.
90 default ROM_SIZE = 256*1024
92 default USE_DCACHE_RAM=1
93 default DCACHE_RAM_BASE=0xffef0000
94 #default DCACHE_RAM_BASE=0xffbf0000
95 #default DCACHE_RAM_BASE=0xfec00000
96 default DCACHE_RAM_SIZE=0x8000
97 default CONFIG_USE_PRINTK_IN_CAR=1
100 ### Leave this to 0; VGA is handled by seperate code.
102 default CONFIG_PCI_ROM_RUN=0
103 default CONFIG_CONSOLE_VGA=0
106 ## Build code for the fallback boot
108 default HAVE_FALLBACK_BOOT=1
111 ## Use TSC for udelay.
113 default CONFIG_UDELAY_TSC=1
114 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
117 ## Build code to reset the motherboard from linuxBIOS
119 default HAVE_HARD_RESET=1
122 ## Build code to export a programmable irq routing table
124 default HAVE_PIRQ_TABLE=1
125 default IRQ_SLOT_COUNT=15
128 ## Build code to export an x86 MP table
129 ## Useful for specifying IRQ routing values
131 default HAVE_MP_TABLE=1
134 ## Build code to load acpi tables
136 default HAVE_ACPI_TABLES=1
139 ## Build code to export a CMOS option table
141 default HAVE_OPTION_TABLE=1
144 ## Build code to fill in tables both in low and high memory
146 default HAVE_LOW_TABLES=1
150 ## Build code to setup a generic IOAPIC
153 default CONFIG_IOAPIC=1
156 ### LinuxBIOS layout values
159 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
160 default ROM_IMAGE_SIZE = 65536
161 default FALLBACK_SIZE = ROM_IMAGE_SIZE
164 ## Use a small 8K stack
166 default STACK_SIZE=0x2000
169 ## Use a small 16K heap
171 default HEAP_SIZE=0x4000
174 ## Only use the option table in a normal image
176 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
177 default USE_OPTION_TABLE = 0
179 default _RAMBASE = 0x00004000
181 default CONFIG_ROM_PAYLOAD = 1
184 ## The default compiler
186 default CROSS_COMPILE=""
187 default CC="$(CROSS_COMPILE)gcc -m32"
191 ## Set this to the max PCI bus number you
192 ## would ever use for PCI config IO.
193 ## Setting this number very high will make
194 ## pci_locate_device take a long time when
195 ## it can't find a device.
197 default CONFIG_MAX_PCI_BUSES = 0x80
200 ## Disable the gdb stub by default
202 default CONFIG_GDB_STUB=0
205 ## The Serial Console
208 # To Enable the Serial Console
209 default CONFIG_CONSOLE_SERIAL8250=1
211 ## Select the serial console baud rate
212 default TTYS0_BAUD=115200
213 #default TTYS0_BAUD=57600
214 #default TTYS0_BAUD=38400
215 #default TTYS0_BAUD=19200
216 #default TTYS0_BAUD=9600
217 #default TTYS0_BAUD=4800
218 #default TTYS0_BAUD=2400
219 #default TTYS0_BAUD=1200
221 # Select the serial console base port
222 default TTYS0_BASE=0x3f8
224 # Select the serial protocol
225 # This defaults to 8 data bits, 1 stop bit, and no parity
226 default TTYS0_LCS=0x3
229 ## Select the coreboot loglevel
231 ## EMERG 1 system is unusable
232 ## ALERT 2 action must be taken immediately
233 ## CRIT 3 critical conditions
234 ## ERR 4 error conditions
235 ## WARNING 5 warning conditions
236 ## NOTICE 6 normal but significant condition
237 ## INFO 7 informational
238 ## DEBUG 8 debug-level messages
239 ## SPEW 9 Way too many details
241 ## Request this level of debugging output
242 default DEFAULT_CONSOLE_LOGLEVEL=5
243 ## At a maximum only compile in this level of debugging
244 default MAXIMUM_CONSOLE_LOGLEVEL=5
249 default CONFIG_CBFS=1