2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2009 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 uses HAVE_OPTION_TABLE
30 uses HAVE_MAINBOARD_RESOURCES
32 uses USE_FALLBACK_IMAGE
33 uses HAVE_FALLBACK_BOOT
37 uses MAINBOARD_PART_NUMBER
38 uses COREBOOT_EXTRA_VERSION
47 uses ROM_SECTION_OFFSET
50 uses CONFIG_ROM_PAYLOAD
51 uses CONFIG_ROM_PAYLOAD_START
52 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
53 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
69 uses DEFAULT_CONSOLE_LOGLEVEL
70 uses MAXIMUM_CONSOLE_LOGLEVEL
71 uses CONFIG_CONSOLE_SERIAL8250
76 uses CONFIG_UDELAY_TSC
77 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
78 uses CONFIG_PCI_ROM_RUN
79 uses CONFIG_CONSOLE_VGA
80 uses CONFIG_MAX_PCI_BUSES
89 uses CONFIG_USE_PRINTK_IN_CAR
91 ## ROM_SIZE is the size of boot ROM that this board will use.
92 default ROM_SIZE = 256*1024
94 default USE_DCACHE_RAM=1
95 default DCACHE_RAM_BASE=0xffef0000
96 #default DCACHE_RAM_BASE=0xffbf0000
97 #default DCACHE_RAM_BASE=0xfec00000
98 default DCACHE_RAM_SIZE=0x8000
99 default CONFIG_USE_PRINTK_IN_CAR=1
102 ### Leave this to 0; VGA is handled by seperate code.
104 default CONFIG_PCI_ROM_RUN=0
105 default CONFIG_CONSOLE_VGA=0
108 ## Build code for the fallback boot
110 default HAVE_FALLBACK_BOOT=1
113 ## Use TSC for udelay.
115 default CONFIG_UDELAY_TSC=1
116 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
119 ## Build code to reset the motherboard from linuxBIOS
121 default HAVE_HARD_RESET=1
124 ## Build code to export a programmable irq routing table
126 default HAVE_PIRQ_TABLE=1
127 default IRQ_SLOT_COUNT=15
130 ## Build code to export an x86 MP table
131 ## Useful for specifying IRQ routing values
133 default HAVE_MP_TABLE=1
136 ## Build code to load acpi tables
138 default HAVE_ACPI_TABLES=1
141 ## Build code to export a CMOS option table
143 default HAVE_OPTION_TABLE=1
146 ## Build code to fill in tables both in low and high memory
148 default HAVE_LOW_TABLES=1
149 default HAVE_HIGH_TABLES=1
150 default HAVE_MAINBOARD_RESOURCES=1
154 ## Build code to setup a generic IOAPIC
157 default CONFIG_IOAPIC=1
160 ### LinuxBIOS layout values
163 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
164 default ROM_IMAGE_SIZE = 65536
165 default FALLBACK_SIZE = 131072
168 ## Use a small 8K stack
170 default STACK_SIZE=0x2000
173 ## Use a small 16K heap
175 default HEAP_SIZE=0x4000
178 ## Only use the option table in a normal image
180 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
181 default USE_OPTION_TABLE = 0
183 default _RAMBASE = 0x00004000
185 default CONFIG_ROM_PAYLOAD = 1
188 ## The default compiler
190 default CROSS_COMPILE=""
191 default CC="$(CROSS_COMPILE)gcc -m32"
195 ## Set this to the max PCI bus number you
196 ## would ever use for PCI config IO.
197 ## Setting this number very high will make
198 ## pci_locate_device take a long time when
199 ## it can't find a device.
201 default CONFIG_MAX_PCI_BUSES = 0x80
204 ## Disable the gdb stub by default
206 default CONFIG_GDB_STUB=0
209 ## The Serial Console
212 # To Enable the Serial Console
213 default CONFIG_CONSOLE_SERIAL8250=1
215 ## Select the serial console baud rate
216 default TTYS0_BAUD=115200
217 #default TTYS0_BAUD=57600
218 #default TTYS0_BAUD=38400
219 #default TTYS0_BAUD=19200
220 #default TTYS0_BAUD=9600
221 #default TTYS0_BAUD=4800
222 #default TTYS0_BAUD=2400
223 #default TTYS0_BAUD=1200
225 # Select the serial console base port
226 default TTYS0_BASE=0x3f8
228 # Select the serial protocol
229 # This defaults to 8 data bits, 1 stop bit, and no parity
230 default TTYS0_LCS=0x3
233 ## Select the coreboot loglevel
235 ## EMERG 1 system is unusable
236 ## ALERT 2 action must be taken immediately
237 ## CRIT 3 critical conditions
238 ## ERR 4 error conditions
239 ## WARNING 5 warning conditions
240 ## NOTICE 6 normal but significant condition
241 ## INFO 7 informational
242 ## DEBUG 8 debug-level messages
243 ## SPEW 9 Way too many details
245 ## Request this level of debugging output
246 default DEFAULT_CONSOLE_LOGLEVEL=5
247 ## At a maximum only compile in this level of debugging
248 default MAXIMUM_CONSOLE_LOGLEVEL=5
253 default CONFIG_CBFS=1