2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2009 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 uses CONFIG_GENERATE_MP_TABLE
23 uses CONFIG_GENERATE_PIRQ_TABLE
24 uses CONFIG_IRQ_SLOT_COUNT
25 uses CONFIG_GENERATE_ACPI_TABLES
26 uses CONFIG_HAVE_OPTION_TABLE
27 uses CONFIG_USE_OPTION_TABLE
28 uses CONFIG_HAVE_LOW_TABLES
30 uses CONFIG_USE_FALLBACK_IMAGE
31 uses CONFIG_HAVE_FALLBACK_BOOT
32 uses CONFIG_HAVE_HARD_RESET
34 uses CONFIG_MAINBOARD_VENDOR
35 uses CONFIG_MAINBOARD_PART_NUMBER
36 uses COREBOOT_EXTRA_VERSION
38 uses CONFIG_FALLBACK_SIZE
39 uses CONFIG_STACK_SIZE
42 uses CONFIG_ROM_SECTION_SIZE
43 uses CONFIG_ROM_IMAGE_SIZE
44 uses CONFIG_ROM_SECTION_SIZE
45 uses CONFIG_ROM_SECTION_OFFSET
48 uses CONFIG_ROM_PAYLOAD
49 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
50 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
54 uses CONFIG_XIP_ROM_SIZE
55 uses CONFIG_XIP_ROM_BASE
58 uses CONFIG_CROSS_COMPILE
64 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
65 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
66 uses CONFIG_CONSOLE_SERIAL8250
67 uses CONFIG_TTYS0_BAUD
68 uses CONFIG_TTYS0_BASE
71 uses CONFIG_UDELAY_TSC
72 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
73 uses CONFIG_PCI_ROM_RUN
74 uses CONFIG_CONSOLE_VGA
75 uses CONFIG_MAX_PCI_BUSES
81 uses CONFIG_USE_DCACHE_RAM
82 uses CONFIG_DCACHE_RAM_BASE
83 uses CONFIG_DCACHE_RAM_SIZE
84 uses CONFIG_USE_PRINTK_IN_CAR
86 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
87 default CONFIG_ROM_SIZE = 256*1024
89 default CONFIG_USE_DCACHE_RAM=1
90 default CONFIG_DCACHE_RAM_BASE=0xffef0000
91 #default CONFIG_DCACHE_RAM_BASE=0xffbf0000
92 #default CONFIG_DCACHE_RAM_BASE=0xfec00000
93 default CONFIG_DCACHE_RAM_SIZE=0x8000
94 default CONFIG_USE_PRINTK_IN_CAR=1
97 ### Leave this to 0; VGA is handled by seperate code.
99 default CONFIG_PCI_ROM_RUN=0
100 default CONFIG_CONSOLE_VGA=0
103 ## Build code for the fallback boot
105 default CONFIG_HAVE_FALLBACK_BOOT=1
108 ## Use TSC for udelay.
110 default CONFIG_UDELAY_TSC=1
111 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
114 ## Build code to reset the motherboard from linuxBIOS
116 default CONFIG_HAVE_HARD_RESET=1
119 ## Build code to export a programmable irq routing table
121 default CONFIG_GENERATE_PIRQ_TABLE=1
122 default CONFIG_IRQ_SLOT_COUNT=15
125 ## Build code to export an x86 MP table
126 ## Useful for specifying IRQ routing values
128 default CONFIG_GENERATE_MP_TABLE=1
131 ## Build code to load acpi tables
133 default CONFIG_GENERATE_ACPI_TABLES=1
136 ## Build code to export a CMOS option table
138 default CONFIG_HAVE_OPTION_TABLE=1
141 ## Build code to fill in tables both in low and high memory
143 default CONFIG_HAVE_LOW_TABLES=1
147 ## Build code to setup a generic IOAPIC
150 default CONFIG_IOAPIC=1
153 ### LinuxBIOS layout values
156 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
157 default CONFIG_ROM_IMAGE_SIZE = 65536
158 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
161 ## Use a small 8K stack
163 default CONFIG_STACK_SIZE=0x2000
166 ## Use a small 16K heap
168 default CONFIG_HEAP_SIZE=0x4000
171 ## Only use the option table in a normal image
173 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
174 default CONFIG_USE_OPTION_TABLE = 0
176 default CONFIG_RAMBASE = 0x00004000
178 default CONFIG_ROM_PAYLOAD = 1
181 ## The default compiler
183 default CONFIG_CROSS_COMPILE=""
184 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
188 ## Set this to the max PCI bus number you
189 ## would ever use for PCI config IO.
190 ## Setting this number very high will make
191 ## pci_locate_device take a long time when
192 ## it can't find a device.
194 default CONFIG_MAX_PCI_BUSES = 0x80
197 ## Disable the gdb stub by default
199 default CONFIG_GDB_STUB=0
202 ## The Serial Console
205 # To Enable the Serial Console
206 default CONFIG_CONSOLE_SERIAL8250=1
208 ## Select the serial console baud rate
209 default CONFIG_TTYS0_BAUD=115200
210 #default CONFIG_TTYS0_BAUD=57600
211 #default CONFIG_TTYS0_BAUD=38400
212 #default CONFIG_TTYS0_BAUD=19200
213 #default CONFIG_TTYS0_BAUD=9600
214 #default CONFIG_TTYS0_BAUD=4800
215 #default CONFIG_TTYS0_BAUD=2400
216 #default CONFIG_TTYS0_BAUD=1200
218 # Select the serial console base port
219 default CONFIG_TTYS0_BASE=0x3f8
221 # Select the serial protocol
222 # This defaults to 8 data bits, 1 stop bit, and no parity
223 default CONFIG_TTYS0_LCS=0x3
226 ## Select the coreboot loglevel
228 ## EMERG 1 system is unusable
229 ## ALERT 2 action must be taken immediately
230 ## CRIT 3 critical conditions
231 ## ERR 4 error conditions
232 ## WARNING 5 warning conditions
233 ## NOTICE 6 normal but significant condition
234 ## INFO 7 informational
235 ## CONFIG_DEBUG 8 debug-level messages
236 ## SPEW 9 Way too many details
238 ## Request this level of debugging output
239 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
240 ## At a maximum only compile in this level of debugging
241 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5