2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 include /config/nofailovercalculation.lb
25 if HAVE_PIRQ_TABLE object irq_tables.o end
26 if HAVE_MP_TABLE object mptable.o end
33 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
34 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
36 makerule ./failover.inc
37 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
38 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
41 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
42 action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
45 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
46 action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
48 mainboardinit cpu/x86/16bit/entry16.inc
49 mainboardinit cpu/x86/32bit/entry32.inc
50 ldscript /cpu/x86/16bit/entry16.lds
51 ldscript /cpu/x86/32bit/entry32.lds
53 mainboardinit cpu/x86/16bit/reset16.inc
54 ldscript /cpu/x86/16bit/reset16.lds
56 mainboardinit cpu/x86/32bit/reset32.inc
57 ldscript /cpu/x86/32bit/reset32.lds
59 mainboardinit arch/i386/lib/cpu_reset.inc
60 mainboardinit arch/i386/lib/id.inc
61 ldscript /arch/i386/lib/id.lds
63 ldscript /arch/i386/lib/failover.lds
64 mainboardinit ./failover.inc
66 mainboardinit cpu/x86/fpu/enable_fpu.inc
67 mainboardinit cpu/x86/mmx/enable_mmx.inc
68 mainboardinit ./auto.inc
69 mainboardinit cpu/x86/mmx/disable_mmx.inc
73 chip northbridge/via/cn700 # Northbridge
74 device pci_domain 0 on # PCI domain
75 device pci 0.0 on end # AGP Bridge
76 device pci 0.1 on end # Error Reporting
77 device pci 0.2 on end # Host Bus Control
78 device pci 0.3 on end # Memory Controller
79 device pci 0.4 on end # Power Management
80 device pci 0.7 on end # V-Link Controller
81 device pci 1.0 on end # PCI Bridge
82 chip southbridge/via/vt8237r # Southbridge
83 # Enable both IDE channels.
84 register "ide0_enable" = "1"
85 register "ide1_enable" = "1"
86 # Both cables are 40pin.
87 register "ide0_80pin_cable" = "0"
88 register "ide1_80pin_cable" = "0"
89 device pci f.0 on end # SATA
90 device pci f.1 on end # IDE
91 register "fn_ctrl_lo" = "0x80"
92 register "fn_ctrl_hi" = "0x1d"
93 device pci 10.0 on end # UHCI
94 device pci 10.1 on end # UHCI
95 device pci 10.2 on end # UHCI
96 device pci 10.3 on end # UHCI
97 device pci 10.4 on end # EHCI
98 device pci 10.5 on end # UDCI
99 device pci 11.0 on # Southbridge LPC
100 chip superio/ite/it8716f # Super I/O
101 device pnp 2e.0 on # Floppy
106 device pnp 2e.1 on # COM1
110 device pnp 2e.2 off # COM2 (N/A on this board)
114 device pnp 2e.3 on # Parallel port
119 device pnp 2e.4 on # Environment controller
124 device pnp 2e.5 off # PS/2 keyboard (not used)
129 device pnp 2e.6 off # PS/2 mouse (not used)
132 device pnp 2e.7 on # GPIO
137 device pnp 2e.8 off # MIDI port (N/A)
141 device pnp 2e.9 off # Game port (N/A)
144 device pnp 2e.a on # Consumer IR
150 device pci 11.5 on end # AC'97 audio
151 # device pci 11.6 off end # AC'97 modem (N/A)
152 device pci 12.0 on end # Ethernet
155 device apic_cluster 0 on # APIC cluster
156 chip cpu/via/model_c7 # VIA C7
157 device apic 0 on end # APIC