1 /* generated by MPTable, version 2.0.15*/
2 /* as modified by RGM for coreboot */
3 #include <console/console.h>
4 #include <arch/smp/mpspec.h>
5 #include <arch/ioapic.h>
6 #include <device/pci.h>
10 static void *smp_write_config_table(void *v)
12 struct mp_config_table *mc;
15 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
17 mptable_init(mc, "EPIA-N ", LAPIC_ADDR);
19 smp_write_processors(mc);
20 mptable_write_buses(mc, NULL, &isa_bus);
22 /*I/O APICs: APIC ID Version State Address*/
23 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
27 dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
29 res = find_resource(dev, PCI_BASE_ADDRESS_0);
31 smp_write_ioapic(mc, 3, 0x20, res->base);
34 dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
36 res = find_resource(dev, PCI_BASE_ADDRESS_0);
38 smp_write_ioapic(mc, 4, 0x20, res->base);
41 dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
43 res = find_resource(dev, PCI_BASE_ADDRESS_0);
45 smp_write_ioapic(mc, 5, 0x20, res->base);
48 dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
50 res = find_resource(dev, PCI_BASE_ADDRESS_0);
52 smp_write_ioapic(mc, 8, 0x20, res->base);
56 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
58 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
59 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
60 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
61 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
62 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
63 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15);
64 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x2, 0x16);
65 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14);
68 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
69 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
70 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
71 /* There is no extension information... */
73 /* Compute the checksums */
74 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
75 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
76 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
77 mc, smp_next_mpe_entry(mc));
78 return smp_next_mpe_entry(mc);
81 unsigned long write_smp_table(unsigned long addr)
84 v = smp_write_floating_table(addr);
85 return (unsigned long)smp_write_config_table(v);