2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009 One Laptop per Child, Association, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
22 default CONFIG_XIP_ROM_SIZE = 64 * 1024
23 include /config/nofailovercalculation.lb
28 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
29 if CONFIG_HAVE_MP_TABLE object mptable.o end
30 if CONFIG_HAVE_ACPI_TABLES
36 # These lines maybe noused.
38 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
39 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
41 makerule ./failover.inc
42 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
43 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
45 if CONFIG_USE_DCACHE_RAM
47 makerule ./cache_as_ram_auto.o
48 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
49 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
52 makerule ./cache_as_ram_auto.inc
53 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
54 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
55 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
56 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
60 mainboardinit cpu/via/16bit/entry16.inc
61 ldscript /cpu/via/16bit/entry16.lds
63 mainboardinit northbridge/via/vx800/romstrap.inc
64 ldscript /northbridge/via/vx800/romstrap.lds
66 mainboardinit cpu/x86/32bit/entry32.inc
67 ldscript /cpu/x86/32bit/entry32.lds
68 if CONFIG_USE_FALLBACK_IMAGE
69 mainboardinit cpu/x86/16bit/reset16.inc
70 ldscript /cpu/x86/16bit/reset16.lds
72 mainboardinit cpu/x86/32bit/reset32.inc
73 ldscript /cpu/x86/32bit/reset32.lds
76 # mainboardinit arch/i386/lib/cpu_reset.inc
77 # Here cpu_reset.inc have label _cpu_reset, which is needed in failover.c,
78 # but cpu_reset.inc also has code to jump to __main() which is not included
79 # in cache_as_ram_auto_auto.c.
81 mainboardinit arch/i386/lib/id.inc
82 ldscript /arch/i386/lib/id.lds
84 if CONFIG_USE_DCACHE_RAM
85 mainboardinit cpu/via/car/cache_as_ram.inc
88 if CONFIG_USE_FALLBACK_IMAGE
89 ldscript /arch/i386/lib/failover.lds
90 # failover.inc need definition in cpu_reset.inc, but we do not include
91 # cpu_reset.inc,so ...
92 # mainboardinit ./failover.inc
94 # mainboardinit cpu/x86/fpu/enable_fpu.inc
95 # mainboardinit cpu/x86/mmx/enable_mmx.inc
97 if CONFIG_USE_DCACHE_RAM
99 initobject cache_as_ram_auto.o
101 mainboardinit ./cache_as_ram_auto.inc
105 # mainboardinit cpu/x86/mmx/disable_mmx.inc
110 chip northbridge/via/vx800 # Northbridge
111 device pci_domain 0 on
112 device pci 0.0 on end # AGP Bridge
113 device pci 0.1 on end # Error Reporting
114 device pci 0.2 on end # Host Bus Control
115 device pci 0.3 on end # Memory Controller
116 device pci 0.4 on end # Power Management
117 device pci 0.7 on end # V-Link Controller
118 device pci 1.0 on end # PCI Bridge
119 # device pci f.0 on end # IDE/SATA
120 # device pci f.1 on end # IDE
121 # device pci 10.0 on end # USB 1.1
122 # device pci 10.1 on end # USB 1.1
123 # device pci 10.2 on end # USB 1.1
124 # device pci 10.4 on end # USB 2.0
125 # device pci 11.0 on # Southbridge LPC
128 device apic_cluster 0 on # APIC cluster
129 chip cpu/via/model_c7 # VIA C7
130 device apic 0 on end # APIC