src/mainboard/via/epia-m/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <device/pci_ids.h>
   4 #if 0
   5 #include <cpu/x86/lapic.h>
   6 #endif
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <arch/hlt.h>
  11 #include <stdlib.h>
  12 #include "pc80/serial.c"
  13 #include "console/console.c"
  14 #include "lib/ramtest.c"
  15 #include "northbridge/via/vt8623/raminit.h"
  16 #include "cpu/x86/mtrr/earlymtrr.c"
  17 #include "cpu/x86/bist.h"
  18 #include "pc80/udelay_io.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "lib/debug.c"
  22 #include "southbridge/via/vt8235/vt8235_early_smbus.c"
  23 #include "southbridge/via/vt8235/vt8235_early_serial.c"
  24
  25 static void memreset_setup(void)
  26 {
  27 }
  28
  29 static inline int spd_read_byte(unsigned device, unsigned address)
  30 {
  31         return smbus_read_byte(device, address);
  32 }
  33
  34 #include "northbridge/via/vt8623/raminit.c"
  35
  36 static void enable_mainboard_devices(void)
  37 {
  38         device_t dev;
  39
  40         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
  41                                 PCI_DEVICE_ID_VIA_8235), 0);
  42
  43         if (dev == PCI_DEV_INVALID) {
  44                 die("Southbridge not found!!!\n");
  45         }
  46         pci_write_config8(dev, 0x50, 0x80);
  47         pci_write_config8(dev, 0x51, 0x1f);
  48 #if 0
  49         // This early setup switches IDE into compatibility mode before PCI gets
  50         // a chance to assign I/Os
  51         // movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
  52         // //      movb    $0x09, %dl
  53         // movb    $0x00, %dl
  54         // PCI_WRITE_CONFIG_BYTE
  55 #endif
  56         /* we do this here as in V2, we can not yet do raw operations
  57          * to pci!
  58          */
  59         dev += 0x100; /* ICKY */
  60
  61         pci_write_config8(dev, 0x04, 7);
  62         pci_write_config8(dev, 0x40, 3);
  63         pci_write_config8(dev, 0x42, 0);
  64         pci_write_config8(dev, 0x3c, 0xe);
  65         pci_write_config8(dev, 0x3d, 0);
  66 }
  67
  68 static void enable_shadow_ram(void)
  69 {
  70         device_t dev = 0; /* no need to look up 0:0.0 */
  71         unsigned char shadowreg;
  72         /* dev 0 for southbridge */
  73         shadowreg = pci_read_config8(dev, 0x63);
  74         /* 0xf0000-0xfffff */
  75         shadowreg |= 0x30;
  76         pci_write_config8(dev, 0x63, shadowreg);
  77 }
  78
  79 static void main(unsigned long bist)
  80 {
  81         device_t dev;
  82
  83         /*
  84          * Enable VGA; 32MB buffer.
  85          */
  86         pci_write_config8(0, 0xe1, 0xdd);
  87
  88         /*
  89          * Disable the firewire stuff, which apparently steps on IO 0+ on
  90          * reset. Doh!
  91          */
  92         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
  93                                 PCI_DEVICE_ID_VIA_6305), 0);
  94         if (dev != PCI_DEV_INVALID) {
  95                 pci_write_config8(dev, 0x15, 0x1c);
  96         }
  97
  98         enable_vt8235_serial();
  99         uart_init();
 100         console_init();
 101
 102         enable_smbus();
 103
 104         print_spew("In romstage.c:main()\n");
 105
 106         /* Halt if there was a built in self test failure */
 107         report_bist_failure(bist);
 108
 109         // init_timer();
 110
 111         outb(5, 0x80);
 112
 113         print_debug(" Enabling mainboard devices\n");
 114         enable_mainboard_devices();
 115
 116         print_debug(" Enabling shadow ram\n");
 117         enable_shadow_ram();
 118
 119         ddr_ram_setup((const struct mem_controller *)0);
 120
 121         /* Check all of memory */
 122 #if 0
 123         ram_check(0x00000000, msr.lo);
 124 #endif
 125 #if 0
 126         static const struct {
 127                 unsigned long lo, hi;
 128         } check_addrs[] = {
 129                 /* Check 16MB of memory @ 0*/
 130                 { 0x00000000, 0x01000000 },
 131 #if TOTAL_CPUS > 1
 132                 /* Check 16MB of memory @ 2GB */
 133                 { 0x80000000, 0x81000000 },
 134 #endif
 135         };
 136         int i;
 137         for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
 138                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 139         }
 140 #endif
 141
 142         if (bist == 0) {
 143                 print_debug(" Doing MTRR init.\n");
 144                 early_mtrr_init();
 145         }
 146
 147         //dump_pci_devices();
 148
 149         print_spew("Leaving romstage.c:main()\n");
 150 }
 151