2 #include <device/pci_def.h>
3 #include <device/pci_ids.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
9 #include "pc80/serial.c"
10 #include "console/console.c"
11 #include "lib/ramtest.c"
12 #include "northbridge/via/vt8623/raminit.h"
13 #include "cpu/x86/mtrr/earlymtrr.c"
14 #include "cpu/x86/bist.h"
15 #include "pc80/udelay_io.c"
16 #include "lib/delay.c"
17 #include "cpu/x86/lapic/boot_cpu.c"
18 #include "lib/debug.c"
19 #include "southbridge/via/vt8235/vt8235_early_smbus.c"
20 #include "southbridge/via/vt8235/vt8235_early_serial.c"
22 static inline int spd_read_byte(unsigned device, unsigned address)
24 return smbus_read_byte(device, address);
27 #include "northbridge/via/vt8623/raminit.c"
29 static void enable_mainboard_devices(void)
33 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
34 PCI_DEVICE_ID_VIA_8235), 0);
36 if (dev == PCI_DEV_INVALID) {
37 die("Southbridge not found!!!\n");
39 pci_write_config8(dev, 0x50, 0x80);
40 pci_write_config8(dev, 0x51, 0x1f);
42 // This early setup switches IDE into compatibility mode before PCI gets
43 // a chance to assign I/Os
44 // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
47 // PCI_WRITE_CONFIG_BYTE
49 /* we do this here as in V2, we can not yet do raw operations
52 dev += 0x100; /* ICKY */
54 pci_write_config8(dev, 0x04, 7);
55 pci_write_config8(dev, 0x40, 3);
56 pci_write_config8(dev, 0x42, 0);
57 pci_write_config8(dev, 0x3c, 0xe);
58 pci_write_config8(dev, 0x3d, 0);
61 static void enable_shadow_ram(void)
63 device_t dev = 0; /* no need to look up 0:0.0 */
64 unsigned char shadowreg;
65 /* dev 0 for southbridge */
66 shadowreg = pci_read_config8(dev, 0x63);
69 pci_write_config8(dev, 0x63, shadowreg);
72 static void main(unsigned long bist)
77 * Enable VGA; 32MB buffer.
79 pci_write_config8(0, 0xe1, 0xdd);
82 * Disable the firewire stuff, which apparently steps on IO 0+ on
85 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
86 PCI_DEVICE_ID_VIA_6305), 0);
87 if (dev != PCI_DEV_INVALID) {
88 pci_write_config8(dev, 0x15, 0x1c);
91 enable_vt8235_serial();
97 print_spew("In romstage.c:main()\n");
99 /* Halt if there was a built in self test failure */
100 report_bist_failure(bist);
106 print_debug(" Enabling mainboard devices\n");
107 enable_mainboard_devices();
109 print_debug(" Enabling shadow ram\n");
112 ddr_ram_setup((const struct mem_controller *)0);
114 /* Check all of memory */
116 ram_check(0x00000000, msr.lo);
119 static const struct {
120 unsigned long lo, hi;
122 /* Check 16MB of memory @ 0*/
123 { 0x00000000, 0x01000000 },
125 /* Check 16MB of memory @ 2GB */
126 { 0x80000000, 0x81000000 },
130 for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
131 ram_check(check_addrs[i].lo, check_addrs[i].hi);
136 print_debug(" Doing MTRR init.\n");
140 //dump_pci_devices();
142 print_spew("Leaving romstage.c:main()\n");