2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_PIRQ_TABLE object irq_tables.o end
60 depends "$(MAINBOARD)/failover.c ./romcc"
61 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
64 makerule ./failover.inc
65 depends "$(MAINBOARD)/failover.c ./romcc"
66 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
70 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
71 action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
74 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
75 action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
79 ## Build our 16 bit and 32 bit linuxBIOS entry code
81 mainboardinit cpu/x86/16bit/entry16.inc
82 mainboardinit cpu/x86/32bit/entry32.inc
83 ldscript /cpu/x86/16bit/entry16.lds
84 ldscript /cpu/x86/32bit/entry32.lds
87 ## Build our reset vector (This is where linuxBIOS is entered)
90 mainboardinit cpu/x86/16bit/reset16.inc
91 ldscript /cpu/x86/16bit/reset16.lds
93 mainboardinit cpu/x86/32bit/reset32.inc
94 ldscript /cpu/x86/32bit/reset32.lds
97 ### Should this be in the northbridge code?
98 mainboardinit arch/i386/lib/cpu_reset.inc
101 ## Include an id string (For safe flashing)
103 mainboardinit arch/i386/lib/id.inc
104 ldscript /arch/i386/lib/id.lds
107 ### This is the early phase of linuxBIOS startup
108 ### Things are delicate and we test to see if we should
109 ### failover to another image.
111 if USE_FALLBACK_IMAGE
112 ldscript /arch/i386/lib/failover.lds
113 mainboardinit ./failover.inc
117 ### O.k. We aren't just an intermediary anymore!
123 mainboardinit cpu/x86/fpu/enable_fpu.inc
124 mainboardinit cpu/x86/mmx/enable_mmx.inc
125 mainboardinit ./auto.inc
126 mainboardinit cpu/x86/mmx/disable_mmx.inc
129 ## Include the secondary Configuration files
134 chip northbridge/via/vt8623
136 device apic_cluster 0 on
137 chip cpu/via/model_centaur
142 device pci_domain 0 on
143 chip southbridge/via/vt8235
145 device pci 10.0 on end # USB 1.1
146 device pci 10.1 on end # USB 1.1
147 device pci 10.2 on end # USB 1.1
148 device pci 10.3 on end # USB 2
150 device pci 11.0 on # Southbridge
151 chip superio/via/vt1211
152 device pnp 2e.0 on # Floppy
157 device pnp 2e.1 on # Parallel Port
162 device pnp 2e.2 on # COM1
166 device pnp 2e.3 on # COM2
170 device pnp 2e.b on # HWM
177 device pci 11.1 on end # IDE
179 device pci 11.5 on end # AC97 Audio
180 device pci 11.6 off end # AC97 Modem
181 device pci 12.0 on end # Ethernet
183 # This is on the EPIA MII, not the M.
184 chip southbridge/ricoh/rl5c476
185 register "enable_cf" = "1"
186 device pci 0a.0 on end
187 device pci 0a.1 on end