2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_PIRQ_TABLE object irq_tables.o end
59 depends "$(MAINBOARD)/failover.c ./romcc"
60 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
63 makerule ./failover.inc
64 depends "$(MAINBOARD)/failover.c ./romcc"
65 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
69 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
70 action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
73 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
74 action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
78 ## Build our 16 bit and 32 bit linuxBIOS entry code
80 mainboardinit cpu/x86/16bit/entry16.inc
81 mainboardinit cpu/x86/32bit/entry32.inc
82 ldscript /cpu/x86/16bit/entry16.lds
83 ldscript /cpu/x86/32bit/entry32.lds
86 ## Build our reset vector (This is where linuxBIOS is entered)
89 mainboardinit cpu/x86/16bit/reset16.inc
90 ldscript /cpu/x86/16bit/reset16.lds
92 mainboardinit cpu/x86/32bit/reset32.inc
93 ldscript /cpu/x86/32bit/reset32.lds
96 ### Should this be in the northbridge code?
97 mainboardinit arch/i386/lib/cpu_reset.inc
100 ## Include an id string (For safe flashing)
102 mainboardinit arch/i386/lib/id.inc
103 ldscript /arch/i386/lib/id.lds
106 ### This is the early phase of linuxBIOS startup
107 ### Things are delicate and we test to see if we should
108 ### failover to another image.
110 if USE_FALLBACK_IMAGE
111 ldscript /arch/i386/lib/failover.lds
112 mainboardinit ./failover.inc
116 ### O.k. We aren't just an intermediary anymore!
122 mainboardinit cpu/x86/fpu/enable_fpu.inc
123 mainboardinit cpu/x86/mmx/enable_mmx.inc
124 mainboardinit ./auto.inc
125 mainboardinit cpu/x86/mmx/disable_mmx.inc
128 ## Include the secondary Configuration files
133 chip northbridge/via/vt8623
134 device pci_domain 0 on
135 chip southbridge/via/vt8235
136 register "enable_usb" = "0"
137 register "enable_native_ide" = "0"
138 register "enable_com_ports" = "1"
139 register "enable_keyboard" = "0"
140 register "enable_nvram" = "1"
142 device pci 10.0 on end # USB 1.1
143 device pci 10.1 on end # USB 1.1
144 device pci 10.2 on end # USB 1.1
145 device pci 10.3 on end # USB 2
147 device pci 11.0 on # Southbridge
148 chip superio/via/vt1211
149 device pnp 2e.0 on # Floppy
154 device pnp 2e.1 off # Parallel Port
159 device pnp 2e.2 on # COM1
163 device pnp 2e.3 on # COM2
167 device pnp 2e.b on # HWM
174 device pci 11.1 on end # IDE
176 device pci 11.5 on end # AC97 Audio
177 device pci 11.6 off end # AC97 Modem
178 device pci 12.0 on end # Ethernet
180 # This is on the EPIA MII, not the M.
181 # chip southbridge/ricoh/rl5c476
185 chip cpu/via/model_centaur