2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 VIA Technologies, Inc.
5 ## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
23 default CONFIG_XIP_ROM_SIZE = 64 * 1024
24 include /config/nofailovercalculation.lb
28 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
29 if CONFIG_GENERATE_MP_TABLE object mptable.o end
30 if CONFIG_GENERATE_ACPI_TABLES
36 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
37 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
39 makerule ./failover.inc
40 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
41 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
44 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
45 action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
48 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
49 action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
51 mainboardinit cpu/x86/16bit/entry16.inc
52 mainboardinit cpu/x86/32bit/entry32.inc
53 ldscript /cpu/x86/16bit/entry16.lds
54 ldscript /cpu/x86/32bit/entry32.lds
55 if CONFIG_USE_FALLBACK_IMAGE
56 mainboardinit cpu/x86/16bit/reset16.inc
57 ldscript /cpu/x86/16bit/reset16.lds
59 mainboardinit cpu/x86/32bit/reset32.inc
60 ldscript /cpu/x86/32bit/reset32.lds
62 mainboardinit arch/i386/lib/cpu_reset.inc
63 mainboardinit arch/i386/lib/id.inc
64 ldscript /arch/i386/lib/id.lds
65 if CONFIG_USE_FALLBACK_IMAGE
66 ldscript /arch/i386/lib/failover.lds
67 mainboardinit ./failover.inc
69 mainboardinit cpu/x86/fpu/enable_fpu.inc
70 mainboardinit cpu/x86/mmx/enable_mmx.inc
71 mainboardinit ./auto.inc
72 mainboardinit cpu/x86/mmx/disable_mmx.inc
76 chip northbridge/via/cn700 # Northbridge
77 device pci_domain 0 on # PCI domain
78 device pci 0.0 on end # AGP Bridge
79 device pci 0.1 on end # Error Reporting
80 device pci 0.2 on end # Host Bus Control
81 device pci 0.3 on end # Memory Controller
82 device pci 0.4 on end # Power Management
83 device pci 0.7 on end # V-Link Controller
84 device pci 1.0 on end # PCI Bridge
85 chip southbridge/via/vt8237r # Southbridge
86 # Enable both IDE channels.
87 register "ide0_enable" = "1"
88 register "ide1_enable" = "1"
89 # Both cables are 40pin.
90 register "ide0_80pin_cable" = "0"
91 register "ide1_80pin_cable" = "0"
92 device pci f.0 on end # IDE
93 register "fn_ctrl_lo" = "0x80"
94 register "fn_ctrl_hi" = "0x1d"
95 device pci 10.0 on end # OHCI
96 device pci 10.1 on end # OHCI
97 device pci 10.2 on end # OHCI
98 device pci 10.3 on end # OHCI
99 device pci 10.4 on end # EHCI
100 device pci 10.5 on end # UDCI
101 device pci 11.0 on # Southbridge LPC
102 chip superio/via/vt1211 # Super I/O
103 device pnp 2e.0 off # Floppy
108 device pnp 2e.1 on # Parallel Port
113 device pnp 2e.2 on # COM1
117 device pnp 2e.3 on # COM2
121 device pnp 2e.b on # HWM
126 device pci 11.5 on end # AC'97 audio
127 # device pci 11.6 off end # AC'97 Modem
128 device pci 12.0 on end # Ethernet
131 device apic_cluster 0 on # APIC cluster
132 chip cpu/via/model_c7 # VIA C7
133 device apic 0 on end # APIC