2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 VIA Technologies, Inc.
5 ## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 include /config/nofailovercalculation.lb
26 if HAVE_PIRQ_TABLE object irq_tables.o end
27 if HAVE_MP_TABLE object mptable.o end
34 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
35 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
37 makerule ./failover.inc
38 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
39 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
42 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
43 action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
46 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
47 action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
49 mainboardinit cpu/x86/16bit/entry16.inc
50 mainboardinit cpu/x86/32bit/entry32.inc
51 ldscript /cpu/x86/16bit/entry16.lds
52 ldscript /cpu/x86/32bit/entry32.lds
54 mainboardinit cpu/x86/16bit/reset16.inc
55 ldscript /cpu/x86/16bit/reset16.lds
57 mainboardinit cpu/x86/32bit/reset32.inc
58 ldscript /cpu/x86/32bit/reset32.lds
60 mainboardinit arch/i386/lib/cpu_reset.inc
61 mainboardinit arch/i386/lib/id.inc
62 ldscript /arch/i386/lib/id.lds
64 ldscript /arch/i386/lib/failover.lds
65 mainboardinit ./failover.inc
67 mainboardinit cpu/x86/fpu/enable_fpu.inc
68 mainboardinit cpu/x86/mmx/enable_mmx.inc
69 mainboardinit ./auto.inc
70 mainboardinit cpu/x86/mmx/disable_mmx.inc
74 chip northbridge/via/cn700 # Northbridge
75 device pci_domain 0 on # PCI domain
76 device pci 0.0 on end # AGP Bridge
77 device pci 0.1 on end # Error Reporting
78 device pci 0.2 on end # Host Bus Control
79 device pci 0.3 on end # Memory Controller
80 device pci 0.4 on end # Power Management
81 device pci 0.7 on end # V-Link Controller
82 device pci 1.0 on end # PCI Bridge
83 chip southbridge/via/vt8237r # Southbridge
84 # Enable both IDE channels.
85 register "ide0_enable" = "1"
86 register "ide1_enable" = "1"
87 # Both cables are 40pin.
88 register "ide0_80pin_cable" = "0"
89 register "ide1_80pin_cable" = "0"
90 device pci f.0 on end # IDE
91 register "fn_ctrl_lo" = "0x80"
92 register "fn_ctrl_hi" = "0x1d"
93 device pci 10.0 on end # OHCI
94 device pci 10.1 on end # OHCI
95 device pci 10.2 on end # OHCI
96 device pci 10.3 on end # OHCI
97 device pci 10.4 on end # EHCI
98 device pci 10.5 on end # UDCI
99 device pci 11.0 on # Southbridge LPC
100 chip superio/via/vt1211 # Super I/O
101 device pnp 2e.0 off # Floppy
106 device pnp 2e.1 on # Parallel Port
111 device pnp 2e.2 on # COM1
115 device pnp 2e.3 on # COM2
119 device pnp 2e.b on # HWM
124 device pci 11.5 on end # AC'97 audio
125 # device pci 11.6 off end # AC'97 Modem
126 device pci 12.0 on end # Ethernet
129 device apic_cluster 0 on # APIC cluster
130 chip cpu/via/model_c7 # VIA C7
131 device apic 0 on end # APIC