2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
5 #include <arch/romcc_io.h>
8 #include "pc80/serial.c"
9 #include "arch/i386/lib/console.c"
10 #include "lib/ramtest.c"
11 #include "northbridge/via/vt8601/raminit.h"
12 #include "cpu/x86/mtrr/earlymtrr.c"
13 #include "cpu/x86/bist.h"
14 #include "pc80/udelay_io.c"
15 #include "lib/delay.c"
16 #include "cpu/x86/lapic/boot_cpu.c"
17 #include "lib/debug.c"
18 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
19 #include "southbridge/via/vt8231/vt8231_early_serial.c"
21 static inline int spd_read_byte(unsigned device, unsigned address)
23 return smbus_read_byte(device, address);
26 #include "northbridge/via/vt8601/raminit.c"
28 #include "lib/generic_sdram.c"
31 static void enable_mainboard_devices(void)
34 /* dev 0 for southbridge */
36 dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
38 if (dev == PCI_DEV_INVALID) {
39 die("Southbridge not found!!!\n");
42 pci_write_config8(dev, 0x50, 7);
43 pci_write_config8(dev, 0x51, 0xff);
45 // This early setup switches IDE into compatibility mode before PCI gets
46 // a chance to assign I/Os
47 // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
50 // PCI_WRITE_CONFIG_BYTE
53 /* we do this here as in V2, we can not yet do raw operations
56 /* changed this to work correctly on later revisions of LB.
57 * The original dev += 0x100; stopped working. It also appears
58 * that if this is not set here, but in ide_init() only, the IDE
59 * does not work at all. I assume it needs to be set before something else,
60 * possibly before enabling the IDE peripheral, or it is a timing issue.
61 * Ben Hewson 29 Apr 2007.
64 dev = pci_locate_device(PCI_ID(0x1106,0x0571), 0);
65 pci_write_config8(dev, 0x42, 0);
68 static void enable_shadow_ram(void)
71 unsigned char shadowreg;
73 shadowreg = pci_read_config8(dev, 0x63);
76 pci_write_config8(dev, 0x63, shadowreg);
79 static void main(unsigned long bist)
86 enable_vt8231_serial();
90 /* Halt if there was a built in self test failure */
91 report_bist_failure(bist);
93 enable_mainboard_devices();
98 this is way more generic than we need.
99 sdram_initialize(ARRAY_SIZE(cpu), cpu);
101 sdram_set_registers((const struct mem_controller *) 0);
102 sdram_set_spd_registers((const struct mem_controller *) 0);
103 sdram_enable(0, (const struct mem_controller *) 0);
105 /* Check all of memory */
107 ram_check(0x00000000, msr.lo);
110 static const struct {
111 unsigned long lo, hi;
113 /* Check 16MB of memory @ 0*/
114 { 0x00000000, 0x01000000 },
116 /* Check 16MB of memory @ 2GB */
117 { 0x80000000, 0x81000000 },
121 for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
122 ram_check(check_addrs[i].lo, check_addrs[i].hi);