5 #include <device/pci_def.h>
6 #include <cpu/p6/apic.h>
8 #include <device/pnp.h>
9 #include <arch/romcc_io.h>
10 #include "pc80/serial.c"
11 #include "arch/i386/lib/console.c"
12 #include "ram/ramtest.c"
13 #include "northbridge/via/vt8601/raminit.h"
16 void udelay(int usecs) {
18 for(i = 0; i < usecs; i++)
22 #include "lib/delay.c"
23 #include "cpu/p6/boot_cpu.c"
26 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
28 #define MAXIMUM_CONSOLE_LOGLEVEL 9
29 #define DEFAULT_CONSOLE_LOGLEVEL 9
31 #include "southbridge/via/vt8231/vt8231_early_serial.c"
32 static void memreset_setup(void)
37 static void memreset(int controllers, const struct mem_controller *ctrl)
41 static inline int spd_read_byte(unsigned device, unsigned address)
44 c = smbus_read_byte(device, address);
50 #include "northbridge/via/vt8601/raminit.c"
52 #include "sdram/generic_sdram.c"
56 enable_mainboard_devices(void) {
58 /* dev 0 for southbridge */
60 dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
62 if (dev == PCI_DEV_INVALID) {
63 die("Southbridge not found!!!\n");
65 pci_write_config8(dev, 0x50, 7);
66 pci_write_config8(dev, 0x51, 0xff);
68 // This early setup switches IDE into compatibility mode before PCI gets
69 // // a chance to assign I/Os
70 // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
73 // PCI_WRITE_CONFIG_BYTE
76 /* we do this here as in V2, we can not yet do raw operations
80 pci_write_config8(dev, 0x42, 0);
84 enable_shadow_ram(void) {
85 device_t dev = 0; /* no need to look up 0:0.0 */
86 unsigned char shadowreg;
87 /* dev 0 for southbridge */
88 shadowreg = pci_read_config8(dev, 0x63);
91 pci_write_config8(dev, 0x63, shadowreg);
93 static void main(void)
99 enable_vt8231_serial();
100 enable_mainboard_devices();
108 this is way more generic than we need.
109 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
111 sdram_set_registers((const struct mem_controller *) 0);
112 sdram_set_spd_registers((const struct mem_controller *) 0);
113 sdram_enable(0, (const struct mem_controller *) 0);
115 /* Check all of memory */
117 ram_check(0x00000000, msr.lo);
120 static const struct {
121 unsigned long lo, hi;
123 /* Check 16MB of memory @ 0*/
124 { 0x00000000, 0x01000000 },
126 /* Check 16MB of memory @ 2GB */
127 { 0x80000000, 0x81000000 },
131 for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
132 ram_check(check_addrs[i].lo, check_addrs[i].hi);