5 #include <device/pci_def.h>
6 #include <cpu/p6/apic.h>
8 #include <device/pnp.h>
9 #include <arch/romcc_io.h>
10 #include "pc80/serial.c"
11 #include "arch/i386/lib/console.c"
12 #include "ram/ramtest.c"
13 #include "northbridge/via/vt8601/raminit.h"
14 void udelay(int usecs) {
16 for(i = 0; i < usecs; i++)
20 #include "lib/delay.c"
21 #include "cpu/p6/boot_cpu.c"
24 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
26 #define MAXIMUM_CONSOLE_LOGLEVEL 9
27 #define DEFAULT_CONSOLE_LOGLEVEL 9
29 static void memreset_setup(void)
34 static void memreset(int controllers, const struct mem_controller *ctrl)
38 static inline int spd_read_byte(unsigned device, unsigned address)
40 return smbus_read_byte(device, address);
45 #include "northbridge/via/vt8601/raminit.c"
46 #include "sdram/generic_sdram.c"
50 static void main(void)
52 struct mem_controller cpu[1];
60 // sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
63 /* Check all of memory */
67 print_debug("TOP_MEM: ");
68 print_debug_hex32(msr.hi);
69 print_debug_hex32(msr.lo);
73 ram_check(0x00000000, msr.lo);
79 /* Check 16MB of memory @ 0*/
80 { 0x00000000, 0x01000000 },
82 /* Check 16MB of memory @ 2GB */
83 { 0x80000000, 0x81000000 },
87 for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
88 ram_check(check_addrs[i].lo, check_addrs[i].hi);