src/mainboard/via/epia/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <arch/hlt.h>
   9 #include "pc80/serial.c"
  10 #include "arch/i386/lib/console.c"
  11 #include "ram/ramtest.c"
  12 #include "northbridge/via/vt8601/raminit.h"
  13 #include "cpu/x86/mtrr/earlymtrr.c"
  14 #include "cpu/x86/bist.h"
  15
  16 /*
  17  */
  18 void udelay(int usecs)
  19 {
  20         int i;
  21         for (i = 0; i < usecs; i++)
  22                 outb(i&0xff, 0x80);
  23 }
  24
  25 #include "lib/delay.c"
  26 #include "cpu/x86/lapic/boot_cpu.c"
  27 #include "debug.c"
  28
  29 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
  30 #include "southbridge/via/vt8231/vt8231_early_serial.c"
  31
  32 static inline int spd_read_byte(unsigned device, unsigned address)
  33 {
  34         unsigned char c;
  35         c = smbus_read_byte(device, address);
  36         return c;
  37 }
  38
  39 #include "northbridge/via/vt8601/raminit.c"
  40 /*
  41   #include "sdram/generic_sdram.c"
  42 */
  43
  44 static void enable_mainboard_devices(void)
  45 {
  46         device_t dev;
  47         /* dev 0 for southbridge */
  48
  49         dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
  50
  51         if (dev == PCI_DEV_INVALID) {
  52                 die("Southbridge not found!!!\n");
  53         }
  54
  55         pci_write_config8(dev, 0x50, 7);
  56         pci_write_config8(dev, 0x51, 0xff);
  57 #if 0
  58         // This early setup switches IDE into compatibility mode before PCI gets
  59         // // a chance to assign I/Os
  60         //         movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
  61         //         //      movb    $0x09, %dl
  62         //                 movb    $0x00, %dl
  63         //                         PCI_WRITE_CONFIG_BYTE
  64         //
  65 #endif
  66         /* we do this here as in V2, we can not yet do raw operations
  67          * to pci!
  68          */
  69         dev += 0x100; /* ICKY */
  70
  71         pci_write_config8(dev, 0x42, 0);
  72 }
  73
  74 static void enable_shadow_ram(void)
  75 {
  76         device_t dev = 0;
  77         unsigned char shadowreg;
  78
  79         shadowreg = pci_read_config8(dev, 0x63);
  80         /* 0xf0000-0xfffff */
  81         shadowreg |= 0x30;
  82         pci_write_config8(dev, 0x63, shadowreg);
  83 }
  84
  85 static void main(unsigned long bist)
  86 {
  87         unsigned long x;
  88
  89         if (bist == 0) {
  90                 early_mtrr_init();
  91         }
  92         enable_vt8231_serial();
  93         uart_init();
  94         console_init();
  95
  96         /* Halt if there was a built in self test failure */
  97         report_bist_failure(bist);
  98
  99         enable_mainboard_devices();
 100         enable_smbus();
 101         enable_shadow_ram();
 102
 103         /*
 104           this is way more generic than we need.
 105           sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 106         */
 107         sdram_set_registers((const struct mem_controller *) 0);
 108         sdram_set_spd_registers((const struct mem_controller *) 0);
 109         sdram_enable(0, (const struct mem_controller *) 0);
 110
 111         /* Check all of memory */
 112 #if 0
 113         ram_check(0x00000000, msr.lo);
 114 #endif
 115 #if 0
 116         static const struct {
 117                 unsigned long lo, hi;
 118         } check_addrs[] = {
 119                 /* Check 16MB of memory @ 0*/
 120                 { 0x00000000, 0x01000000 },
 121 #if TOTAL_CPUS > 1
 122                 /* Check 16MB of memory @ 2GB */
 123                 { 0x80000000, 0x81000000 },
 124 #endif
 125         };
 126         int i;
 127         for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
 128                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 129         }
 130 #endif
 131 }