src/mainboard/via/epia/auto.c

   1 #define ASSEMBLY 1
   2
   3 //#define MAXIMUM_CONSOLE_LOGLEVEL 6
   4 //#define DEFAULT_CONSOLE_LOGLEVEL 6
   5
   6 #include <stdint.h>
   7 #include <device/pci_def.h>
   8 #include <cpu/p6/apic.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <arch/hlt.h>
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16 #include "northbridge/via/vt8601/raminit.h"
  17 #include "cpu/p6/earlymtrr.c"
  18 /*
  19  */
  20 void udelay(int usecs)
  21 {
  22         int i;
  23         for(i = 0; i < usecs; i++)
  24                 outb(i&0xff, 0x80);
  25 }
  26
  27 #include "lib/delay.c"
  28 #include "cpu/p6/boot_cpu.c"
  29 #include "debug.c"
  30
  31 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
  32
  33
  34 #include "southbridge/via/vt8231/vt8231_early_serial.c"
  35 static void memreset_setup(void)
  36 {
  37 }
  38
  39 /*
  40   static void memreset(int controllers, const struct mem_controller *ctrl)
  41   {
  42   }
  43 */
  44 static inline int spd_read_byte(unsigned device, unsigned address)
  45 {
  46         unsigned char c;
  47         c = smbus_read_byte(device, address);
  48         return c;
  49 }
  50
  51
  52
  53 #include "northbridge/via/vt8601/raminit.c"
  54 /*
  55   #include "sdram/generic_sdram.c"
  56 */
  57
  58 static void enable_mainboard_devices(void)
  59 {
  60         device_t dev;
  61         /* dev 0 for southbridge */
  62
  63         dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
  64
  65         if (dev == PCI_DEV_INVALID) {
  66                 die("Southbridge not found!!!\n");
  67         }
  68         pci_write_config8(dev, 0x50, 7);
  69         pci_write_config8(dev, 0x51, 0xff);
  70 #if 0
  71         // This early setup switches IDE into compatibility mode before PCI gets
  72         // // a chance to assign I/Os
  73         //         movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
  74         //         //      movb    $0x09, %dl
  75         //                 movb    $0x00, %dl
  76         //                         PCI_WRITE_CONFIG_BYTE
  77         //
  78 #endif
  79         /* we do this here as in V2, we can not yet do raw operations
  80          * to pci!
  81          */
  82         dev += 0x100; /* ICKY */
  83
  84         pci_write_config8(dev, 0x42, 0);
  85 }
  86
  87 static void enable_shadow_ram(void)
  88 {
  89         device_t dev = 0; /* no need to look up 0:0.0 */
  90         unsigned char shadowreg;
  91         /* dev 0 for southbridge */
  92         shadowreg = pci_read_config8(dev, 0x63);
  93         /* 0xf0000-0xfffff */
  94         shadowreg |= 0x30;
  95         pci_write_config8(dev, 0x63, shadowreg);
  96 }
  97
  98 static void main(void)
  99 {
 100         unsigned long x;
 101         /*      init_timer();*/
 102         outb(5, 0x80);
 103
 104         enable_vt8231_serial();
 105
 106         uart_init();
 107         console_init();
 108
 109         enable_mainboard_devices();
 110         enable_smbus();
 111         enable_shadow_ram();
 112         /*
 113           memreset_setup();
 114           this is way more generic than we need.
 115           sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 116         */
 117         sdram_set_registers((const struct mem_controller *) 0);
 118         sdram_set_spd_registers((const struct mem_controller *) 0);
 119         sdram_enable(0, (const struct mem_controller *) 0);
 120
 121         /* Check all of memory */
 122 #if 0
 123         ram_check(0x00000000, msr.lo);
 124 #endif
 125 #if 0
 126         static const struct {
 127                 unsigned long lo, hi;
 128         } check_addrs[] = {
 129                 /* Check 16MB of memory @ 0*/
 130                 { 0x00000000, 0x01000000 },
 131 #if TOTAL_CPUS > 1
 132                 /* Check 16MB of memory @ 2GB */
 133                 { 0x80000000, 0x81000000 },
 134 #endif
 135         };
 136         int i;
 137         for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
 138                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 139         }
 140 #endif
 141         early_mtrr_init();
 142 }