5 #include <device/pci_def.h>
6 #include <cpu/p6/apic.h>
8 #include <device/pnp.h>
9 #include <arch/romcc_io.h>
10 #include "pc80/serial.c"
11 #include "arch/i386/lib/console.c"
12 #include "ram/ramtest.c"
13 #include "northbridge/via/vt8601/raminit.h"
16 void udelay(int usecs) {
18 for(i = 0; i < usecs; i++)
22 #include "lib/delay.c"
23 #include "cpu/p6/boot_cpu.c"
26 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
28 #define MAXIMUM_CONSOLE_LOGLEVEL 9
29 #define DEFAULT_CONSOLE_LOGLEVEL 9
31 #include "southbridge/via/vt8231/vt8231_early_serial.c"
32 static void memreset_setup(void)
37 static void memreset(int controllers, const struct mem_controller *ctrl)
41 static inline int spd_read_byte(unsigned device, unsigned address)
43 return smbus_read_byte(device, address);
48 #include "northbridge/via/vt8601/raminit.c"
50 #include "sdram/generic_sdram.c"
53 static void main(void)
59 enable_vt8231_serial();
66 this is way more generic than we need.
67 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
69 sdram_set_registers((const struct mem_controller *) 0);
72 /* Check all of memory */
76 print_debug("TOP_MEM: ");
77 print_debug_hex32(msr.hi);
78 print_debug_hex32(msr.lo);
82 ram_check(0x00000000, msr.lo);
88 /* Check 16MB of memory @ 0*/
89 { 0x00000000, 0x01000000 },
91 /* Check 16MB of memory @ 2GB */
92 { 0x80000000, 0x81000000 },
96 for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
97 ram_check(check_addrs[i].lo, check_addrs[i].hi);