3 //#define MAXIMUM_CONSOLE_LOGLEVEL 6
4 //#define DEFAULT_CONSOLE_LOGLEVEL 6
7 #include <device/pci_def.h>
8 #include <cpu/p6/apic.h>
10 #include <device/pnp.h>
11 #include <arch/romcc_io.h>
12 #include "pc80/serial.c"
13 #include "arch/i386/lib/console.c"
14 #include "ram/ramtest.c"
15 #include "northbridge/via/vt8601/raminit.h"
16 #include "cpu/p6/earlymtrr.c"
19 void udelay(int usecs)
22 for(i = 0; i < usecs; i++)
26 #include "lib/delay.c"
27 #include "cpu/p6/boot_cpu.c"
30 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
33 #include "southbridge/via/vt8231/vt8231_early_serial.c"
34 static void memreset_setup(void)
39 static void memreset(int controllers, const struct mem_controller *ctrl)
43 static inline int spd_read_byte(unsigned device, unsigned address)
46 c = smbus_read_byte(device, address);
52 #include "northbridge/via/vt8601/raminit.c"
54 #include "sdram/generic_sdram.c"
57 static void enable_mainboard_devices(void)
60 /* dev 0 for southbridge */
62 dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
64 if (dev == PCI_DEV_INVALID) {
65 die("Southbridge not found!!!\n");
67 pci_write_config8(dev, 0x50, 7);
68 pci_write_config8(dev, 0x51, 0xff);
70 // This early setup switches IDE into compatibility mode before PCI gets
71 // // a chance to assign I/Os
72 // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
75 // PCI_WRITE_CONFIG_BYTE
78 /* we do this here as in V2, we can not yet do raw operations
81 dev += 0x100; /* ICKY */
83 pci_write_config8(dev, 0x42, 0);
86 static void enable_shadow_ram(void)
88 device_t dev = 0; /* no need to look up 0:0.0 */
89 unsigned char shadowreg;
90 /* dev 0 for southbridge */
91 shadowreg = pci_read_config8(dev, 0x63);
94 pci_write_config8(dev, 0x63, shadowreg);
97 static void main(void)
103 enable_vt8231_serial();
108 enable_mainboard_devices();
113 this is way more generic than we need.
114 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
116 sdram_set_registers((const struct mem_controller *) 0);
117 sdram_set_spd_registers((const struct mem_controller *) 0);
118 sdram_enable(0, (const struct mem_controller *) 0);
120 /* Check all of memory */
122 ram_check(0x00000000, msr.lo);
125 static const struct {
126 unsigned long lo, hi;
128 /* Check 16MB of memory @ 0*/
129 { 0x00000000, 0x01000000 },
131 /* Check 16MB of memory @ 2GB */
132 { 0x80000000, 0x81000000 },
136 for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
137 ram_check(check_addrs[i].lo, check_addrs[i].hi);