4 #include <device/pci_def.h>
6 #include <cpu/x86/lapic.h>
9 #include <device/pnp_def.h>
10 #include <arch/romcc_io.h>
12 #include "pc80/serial.c"
13 #include "arch/i386/lib/console.c"
14 #include "ram/ramtest.c"
15 #include "northbridge/via/vt8601/raminit.h"
16 #include "cpu/x86/mtrr/earlymtrr.c"
17 #include "cpu/x86/bist.h"
21 void udelay(int usecs)
24 for(i = 0; i < usecs; i++)
28 #include "lib/delay.c"
29 #include "cpu/x86/lapic/boot_cpu.c"
32 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
35 #include "southbridge/via/vt8231/vt8231_early_serial.c"
36 static void memreset_setup(void)
41 static void memreset(int controllers, const struct mem_controller *ctrl)
45 static inline int spd_read_byte(unsigned device, unsigned address)
48 c = smbus_read_byte(device, address);
54 #include "northbridge/via/vt8601/raminit.c"
56 #include "sdram/generic_sdram.c"
59 static void enable_mainboard_devices(void)
62 /* dev 0 for southbridge */
64 dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
66 if (dev == PCI_DEV_INVALID) {
67 die("Southbridge not found!!!\n");
69 pci_write_config8(dev, 0x50, 7);
70 pci_write_config8(dev, 0x51, 0xff);
72 // This early setup switches IDE into compatibility mode before PCI gets
73 // // a chance to assign I/Os
74 // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
77 // PCI_WRITE_CONFIG_BYTE
80 /* we do this here as in V2, we can not yet do raw operations
83 dev += 0x100; /* ICKY */
85 pci_write_config8(dev, 0x42, 0);
88 static void enable_shadow_ram(void)
90 device_t dev = 0; /* no need to look up 0:0.0 */
91 unsigned char shadowreg;
92 /* dev 0 for southbridge */
93 shadowreg = pci_read_config8(dev, 0x63);
96 pci_write_config8(dev, 0x63, shadowreg);
99 static void main(unsigned long bist)
106 enable_vt8231_serial();
110 /* Halt if there was a built in self test failure */
111 report_bist_failure(bist);
113 enable_mainboard_devices();
118 this is way more generic than we need.
119 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
121 sdram_set_registers((const struct mem_controller *) 0);
122 sdram_set_spd_registers((const struct mem_controller *) 0);
123 sdram_enable(0, (const struct mem_controller *) 0);
125 /* Check all of memory */
127 ram_check(0x00000000, msr.lo);
130 static const struct {
131 unsigned long lo, hi;
133 /* Check 16MB of memory @ 0*/
134 { 0x00000000, 0x01000000 },
136 /* Check 16MB of memory @ 2GB */
137 { 0x80000000, 0x81000000 },
141 for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
142 ram_check(check_addrs[i].lo, check_addrs[i].hi);