5 #include <device/pci_def.h>
6 #include <cpu/p6/apic.h>
8 #include <device/pnp.h>
9 #include <arch/romcc_io.h>
10 #include "pc80/serial.c"
11 #include "arch/i386/lib/console.c"
12 #include "ram/ramtest.c"
13 #include "northbridge/via/vt8601/raminit.h"
16 void udelay(int usecs)
19 for(i = 0; i < usecs; i++)
23 #include "lib/delay.c"
24 #include "cpu/p6/boot_cpu.c"
27 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
29 #define MAXIMUM_CONSOLE_LOGLEVEL 6
30 #define DEFAULT_CONSOLE_LOGLEVEL 6
32 #include "southbridge/via/vt8231/vt8231_early_serial.c"
33 static void memreset_setup(void)
38 static void memreset(int controllers, const struct mem_controller *ctrl)
42 static inline int spd_read_byte(unsigned device, unsigned address)
45 c = smbus_read_byte(device, address);
51 #include "northbridge/via/vt8601/raminit.c"
53 #include "sdram/generic_sdram.c"
56 static void enable_mainboard_devices(void)
59 /* dev 0 for southbridge */
61 dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
63 if (dev == PCI_DEV_INVALID) {
64 die("Southbridge not found!!!\n");
66 pci_write_config8(dev, 0x50, 7);
67 pci_write_config8(dev, 0x51, 0xff);
69 // This early setup switches IDE into compatibility mode before PCI gets
70 // // a chance to assign I/Os
71 // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
74 // PCI_WRITE_CONFIG_BYTE
77 /* we do this here as in V2, we can not yet do raw operations
81 pci_write_config8(dev, 0x42, 0);
84 static void enable_shadow_ram(void)
86 device_t dev = 0; /* no need to look up 0:0.0 */
87 unsigned char shadowreg;
88 /* dev 0 for southbridge */
89 shadowreg = pci_read_config8(dev, 0x63);
92 pci_write_config8(dev, 0x63, shadowreg);
95 static void main(void)
101 enable_vt8231_serial();
102 enable_mainboard_devices();
110 this is way more generic than we need.
111 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
113 sdram_set_registers((const struct mem_controller *) 0);
114 sdram_set_spd_registers((const struct mem_controller *) 0);
115 sdram_enable(0, (const struct mem_controller *) 0);
117 /* Check all of memory */
119 ram_check(0x00000000, msr.lo);
122 static const struct {
123 unsigned long lo, hi;
125 /* Check 16MB of memory @ 0*/
126 { 0x00000000, 0x01000000 },
128 /* Check 16MB of memory @ 2GB */
129 { 0x80000000, 0x81000000 },
133 for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
134 ram_check(check_addrs[i].lo, check_addrs[i].hi);