src/mainboard/via/epia/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <cpu/p6/apic.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <arch/hlt.h>
  10 #include "pc80/serial.c"
  11 #include "arch/i386/lib/console.c"
  12 #include "ram/ramtest.c"
  13 #include "northbridge/via/vt8601/raminit.h"
  14 #include "cpu/p6/earlymtrr.c"
  15
  16 /*
  17  */
  18 void udelay(int usecs)
  19 {
  20         int i;
  21         for(i = 0; i < usecs; i++)
  22                 outb(i&0xff, 0x80);
  23 }
  24
  25 #include "lib/delay.c"
  26 #include "cpu/p6/boot_cpu.c"
  27 #include "debug.c"
  28
  29 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
  30
  31
  32 #include "southbridge/via/vt8231/vt8231_early_serial.c"
  33 static void memreset_setup(void)
  34 {
  35 }
  36
  37 /*
  38   static void memreset(int controllers, const struct mem_controller *ctrl)
  39   {
  40   }
  41 */
  42 static inline int spd_read_byte(unsigned device, unsigned address)
  43 {
  44         unsigned char c;
  45         c = smbus_read_byte(device, address);
  46         return c;
  47 }
  48
  49
  50
  51 #include "northbridge/via/vt8601/raminit.c"
  52 /*
  53   #include "sdram/generic_sdram.c"
  54 */
  55
  56 static void enable_mainboard_devices(void)
  57 {
  58         device_t dev;
  59         /* dev 0 for southbridge */
  60
  61         dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
  62
  63         if (dev == PCI_DEV_INVALID) {
  64                 die("Southbridge not found!!!\n");
  65         }
  66         pci_write_config8(dev, 0x50, 7);
  67         pci_write_config8(dev, 0x51, 0xff);
  68 #if 0
  69         // This early setup switches IDE into compatibility mode before PCI gets
  70         // // a chance to assign I/Os
  71         //         movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
  72         //         //      movb    $0x09, %dl
  73         //                 movb    $0x00, %dl
  74         //                         PCI_WRITE_CONFIG_BYTE
  75         //
  76 #endif
  77         /* we do this here as in V2, we can not yet do raw operations
  78          * to pci!
  79          */
  80         dev += 0x100; /* ICKY */
  81
  82         pci_write_config8(dev, 0x42, 0);
  83 }
  84
  85 static void enable_shadow_ram(void)
  86 {
  87         device_t dev = 0; /* no need to look up 0:0.0 */
  88         unsigned char shadowreg;
  89         /* dev 0 for southbridge */
  90         shadowreg = pci_read_config8(dev, 0x63);
  91         /* 0xf0000-0xfffff */
  92         shadowreg |= 0x30;
  93         pci_write_config8(dev, 0x63, shadowreg);
  94 }
  95
  96 static void main(void)
  97 {
  98         unsigned long x;
  99         /*      init_timer();*/
 100         outb(5, 0x80);
 101
 102         enable_vt8231_serial();
 103
 104         uart_init();
 105         console_init();
 106
 107         enable_mainboard_devices();
 108         enable_smbus();
 109         enable_shadow_ram();
 110         /*
 111           memreset_setup();
 112           this is way more generic than we need.
 113           sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 114         */
 115         sdram_set_registers((const struct mem_controller *) 0);
 116         sdram_set_spd_registers((const struct mem_controller *) 0);
 117         sdram_enable(0, (const struct mem_controller *) 0);
 118
 119         /* Check all of memory */
 120 #if 0
 121         ram_check(0x00000000, msr.lo);
 122 #endif
 123 #if 0
 124         static const struct {
 125                 unsigned long lo, hi;
 126         } check_addrs[] = {
 127                 /* Check 16MB of memory @ 0*/
 128                 { 0x00000000, 0x01000000 },
 129 #if TOTAL_CPUS > 1
 130                 /* Check 16MB of memory @ 2GB */
 131                 { 0x80000000, 0x81000000 },
 132 #endif
 133         };
 134         int i;
 135         for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
 136                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 137         }
 138 #endif
 139         early_mtrr_init();
 140 }