1 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
2 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
3 uses CONFIG_CONSOLE_SERIAL8250
7 uses CONFIG_GENERATE_MP_TABLE
8 uses CONFIG_GENERATE_PIRQ_TABLE
9 uses CONFIG_USE_FALLBACK_IMAGE
10 uses CONFIG_HAVE_FALLBACK_BOOT
11 uses CONFIG_HAVE_HARD_RESET
13 uses CONFIG_UDELAY_TSC
14 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
15 uses CONFIG_HAVE_OPTION_TABLE
16 uses CONFIG_USE_OPTION_TABLE
17 uses CONFIG_ROM_PAYLOAD
18 uses CONFIG_IRQ_SLOT_COUNT
20 uses CONFIG_MAINBOARD_VENDOR
21 uses CONFIG_MAINBOARD_PART_NUMBER
22 uses COREBOOT_EXTRA_VERSION
24 uses CONFIG_FALLBACK_SIZE
25 uses CONFIG_STACK_SIZE
28 uses CONFIG_ROM_SECTION_SIZE
29 uses CONFIG_ROM_IMAGE_SIZE
30 uses CONFIG_ROM_SECTION_SIZE
31 uses CONFIG_ROM_SECTION_OFFSET
32 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
33 uses CONFIG_PRECOMPRESSED_PAYLOAD
36 uses CONFIG_XIP_ROM_SIZE
37 uses CONFIG_XIP_ROM_BASE
38 uses CONFIG_GENERATE_MP_TABLE
39 uses CONFIG_CROSS_COMPILE
45 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
46 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
49 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
50 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
52 default CONFIG_CONSOLE_SERIAL8250=1
53 ## Select the serial console baud rate
54 default CONFIG_TTYS0_BAUD=115200
56 # Select the serial console base port
57 default CONFIG_TTYS0_BASE=0x3f8
59 # Select the serial protocol
60 # This defaults to 8 data bits, 1 stop bit, and no parity
61 default CONFIG_TTYS0_LCS=0x3
63 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
64 default CONFIG_ROM_SIZE = 256*1024
71 ## Build code for the fallback boot
73 default CONFIG_HAVE_FALLBACK_BOOT=1
78 default CONFIG_GENERATE_MP_TABLE=0
81 ## Build code to reset the motherboard from coreboot
83 default CONFIG_HAVE_HARD_RESET=0
86 ## use io based udelay function
87 ## disable IO and enable TSC on Nehemiah boards
89 default CONFIG_UDELAY_IO=1
90 default CONFIG_UDELAY_TSC=0
91 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
94 ## Build code to export a programmable irq routing table
96 default CONFIG_GENERATE_PIRQ_TABLE=1
97 default CONFIG_IRQ_SLOT_COUNT=5
101 ## Build code to export a CMOS option table
103 default CONFIG_HAVE_OPTION_TABLE=1
106 ### coreboot layout values
109 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
110 default CONFIG_ROM_IMAGE_SIZE = 65536
111 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
114 ## Use a small 8K stack
116 default CONFIG_STACK_SIZE=0x2000
119 ## Use a small 16K heap
121 default CONFIG_HEAP_SIZE=0x4000
124 ## Only use the option table in a normal image
126 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
127 default CONFIG_USE_OPTION_TABLE = 0
129 default CONFIG_RAMBASE = 0x00004000
131 default CONFIG_ROM_PAYLOAD = 1
134 ## The default compiler
136 default CONFIG_CROSS_COMPILE=""
137 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"