3 uses USE_FALLBACK_IMAGE
11 uses ROM_SECTION_OFFSET
12 uses CONFIG_ROM_STREAM_START
19 ## ROM_SIZE is the size of boot ROM that this board will use.
20 default ROM_SIZE 256*1024
27 ## Build code for the fallback boot
29 option HAVE_FALLBACK_BOOT=1
34 option HAVE_MP_TABLE=0
37 ## Build code to reset the motherboard from linuxBIOS
39 option HAVE_HARD_RESET=1
42 ## Build code to export a programmable irq routing table
44 option HAVE_PIRQ_TABLE=1
45 option IRQ_SLOT_COUNT=5
49 ## Build code to export a CMOS option table
51 option HAVE_OPTION_TABLE=1
54 ### LinuxBIOS layout values
57 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
58 option ROM_IMAGE_SIZE = 65536
61 ## Use a small 8K stack
63 option STACK_SIZE=0x2000
66 ## Use a small 16K heap
68 option HEAP_SIZE=0x4000
71 ## Only use the option table in a normal image
73 option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
76 ## Compute the location and size of where this firmware image
77 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
80 option ROM_SECTION_SIZE = FALLBACK_SIZE
81 option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
83 option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
84 option ROM_SECTION_OFFSET = 0
88 ## Compute the start location and size size of
89 ## The linuxBIOS bootloader.
91 option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
92 option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
93 option CONFIG_ROM_STREAM = 1
96 ## Compute where this copy of linuxBIOS will start in the boot rom
98 option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
101 ## Compute a range of ROM that can cached to speed up linuxBIOS,
104 ## XIP_ROM_SIZE must be a power of 2.
105 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
107 option XIP_ROM_SIZE=65536
108 option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
111 ## Set all of the defaults for an x86 architecture
117 ## Build the objects we have code for in this directory.
127 makerule ./failover.E
128 depends "$(MAINBOARD)/failover.c"
129 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
132 makerule ./failover.inc
133 depends "./failover.E ./romcc"
134 action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
138 depends "$(MAINBOARD)/auto.c"
139 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
142 depends "./auto.E ./romcc"
143 action "./romcc -O -mcpu=c3 ./auto.E "
147 ## Build our 16 bit and 32 bit linuxBIOS entry code
149 mainboardinit cpu/i386/entry16.inc
150 mainboardinit cpu/i386/entry32.inc
151 ldscript /cpu/i386/entry16.lds
152 ldscript /cpu/i386/entry32.lds
155 ## Build our reset vector (This is where linuxBIOS is entered)
157 if USE_FALLBACK_IMAGE
158 mainboardinit cpu/i386/reset16.inc
159 ldscript /cpu/i386/reset16.lds
161 mainboardinit cpu/i386/reset32.inc
162 ldscript /cpu/i386/reset32.lds
165 ### Should this be in the northbridge code?
166 mainboardinit arch/i386/lib/cpu_reset.inc
169 ## Include an id string (For safe flashing)
171 mainboardinit arch/i386/lib/id.inc
172 ldscript /arch/i386/lib/id.lds
177 # mainboardinit cpu/p6/earlymtrr.inc
180 ### This is the early phase of linuxBIOS startup
181 ### Things are delicate and we test to see if we should
182 ### failover to another image.
184 if USE_FALLBACK_IMAGE
185 ldscript /arch/i386/lib/failover.lds
186 mainboardinit ./failover.inc
190 ### O.k. We aren't just an intermediary anymore!
196 mainboardinit ./auto.inc
199 ## Include the secondary Configuration files
204 northbridge via/vt8601 "vt8601"
207 southbridge via/vt8231 "vt8231"
216 register "enable_usb" = "0"
217 register "enable_native_ide" = "0"
218 register "enable_com_ports" = "1"
219 register "enable_keyboard" = "0"
220 register "enable_nvram" = "1"
229 ## Include the old serial code for those few places that still need it.
231 mainboardinit pc80/serial.inc
232 mainboardinit arch/i386/lib/console.inc