2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
19 default CONFIG_ROM_STREAM = 1
22 ## Compute where this copy of linuxBIOS will start in the boot rom
24 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
27 ## Compute a range of ROM that can cached to speed up linuxBIOS,
30 ## XIP_ROM_SIZE must be a power of 2.
31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
33 default XIP_ROM_SIZE=65536
34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
37 ## Set all of the defaults for an x86 architecture
43 ## Build the objects we have code for in this directory.
54 depends "$(MAINBOARD)/failover.c"
55 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
58 makerule ./failover.inc
59 depends "./failover.E ./romcc"
60 action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
64 depends "$(MAINBOARD)/auto.c"
65 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
68 depends "./auto.E ./romcc"
69 action "./romcc -O -mcpu=c3 ./auto.E "
73 ## Build our 16 bit and 32 bit linuxBIOS entry code
75 mainboardinit cpu/x86/16bit/entry16.inc
76 mainboardinit cpu/x86/32bit/entry32.inc
77 ldscript /cpu/x86/16bit/entry16.lds
78 ldscript /cpu/x86/32bit/entry32.lds
81 ## Build our reset vector (This is where linuxBIOS is entered)
84 mainboardinit cpu/x86/16bit/reset16.inc
85 ldscript /cpu/x86/16bit/reset16.lds
87 mainboardinit cpu/x86/32bit/reset32.inc
88 ldscript /cpu/x86/32bit/reset32.lds
91 ### Should this be in the northbridge code?
92 mainboardinit arch/i386/lib/cpu_reset.inc
95 ## Include an id string (For safe flashing)
97 mainboardinit arch/i386/lib/id.inc
98 ldscript /arch/i386/lib/id.lds
103 # mainboardinit cpu/p6/earlymtrr.inc
106 ### This is the early phase of linuxBIOS startup
107 ### Things are delicate and we test to see if we should
108 ### failover to another image.
110 if USE_FALLBACK_IMAGE
111 ldscript /arch/i386/lib/failover.lds
112 mainboardinit ./failover.inc
116 ### O.k. We aren't just an intermediary anymore!
122 mainboardinit ./auto.inc
125 ## Include the secondary Configuration files
130 chip northbridge/via/vt8601
133 chip southbridge/via/vt8231
142 register "enable_usb" = "0"
143 register "enable_native_ide" = "0"
144 register "enable_com_ports" = "1"
145 register "enable_keyboard" = "0"
146 register "enable_nvram" = "1"
147 chip superio/winbond/w83627hf
148 device pnp 2e.0 on # Floppy
153 device pnp 2e.1 off # Parallel Port
157 device pnp 2e.2 on # Com1
161 device pnp 2e.3 off # Com2
165 device pnp 2e.5 on # Keyboard
171 device pnp 2e.6 off end # CIR
172 device pnp 2e.7 off end # GAME_MIDI_GIPO1
173 device pnp 2e.8 off end # GPIO2
174 device pnp 2e.9 off end # GPIO3
175 device pnp 2e.a off end # ACPI
176 device pnp 2e.b on # HW Monitor
179 register "com1" = "{1}"
180 # register "com1" = "{1, 0, 0x3f8, 4}"
181 # register "lpt" = "{1}"
187 ## Include the old serial code for those few places that still need it.
189 mainboardinit pc80/serial.inc
190 mainboardinit arch/i386/lib/console.inc