2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
18 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_PIRQ_TABLE object irq_tables.o end
53 depends "$(MAINBOARD)/failover.c ./romcc"
54 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
57 makerule ./failover.inc
58 depends "$(MAINBOARD)/failover.c ./romcc"
59 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
63 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
64 action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
67 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
68 action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
72 ## Build our 16 bit and 32 bit linuxBIOS entry code
74 mainboardinit cpu/x86/16bit/entry16.inc
75 mainboardinit cpu/x86/32bit/entry32.inc
76 ldscript /cpu/x86/16bit/entry16.lds
77 ldscript /cpu/x86/32bit/entry32.lds
80 ## Build our reset vector (This is where linuxBIOS is entered)
83 mainboardinit cpu/x86/16bit/reset16.inc
84 ldscript /cpu/x86/16bit/reset16.lds
86 mainboardinit cpu/x86/32bit/reset32.inc
87 ldscript /cpu/x86/32bit/reset32.lds
90 ### Should this be in the northbridge code?
91 mainboardinit arch/i386/lib/cpu_reset.inc
94 ## Include an id string (For safe flashing)
96 mainboardinit arch/i386/lib/id.inc
97 ldscript /arch/i386/lib/id.lds
100 ### This is the early phase of linuxBIOS startup
101 ### Things are delicate and we test to see if we should
102 ### failover to another image.
104 if USE_FALLBACK_IMAGE
105 ldscript /arch/i386/lib/failover.lds
106 mainboardinit ./failover.inc
110 ### O.k. We aren't just an intermediary anymore!
116 mainboardinit cpu/x86/fpu/enable_fpu.inc
117 mainboardinit cpu/x86/mmx/enable_mmx.inc
118 mainboardinit ./auto.inc
119 mainboardinit cpu/x86/mmx/disable_mmx.inc
122 ## Include the secondary Configuration files
127 chip northbridge/via/vt8601
128 device pci_domain 0 on
129 device pci 0.0 on end # Northbridge
130 device pci 0.1 on # AGP bridge
131 # chip drivers/pci/onboard # Integrated VGA
132 # device pci 0.0 on end
133 # register "rom_adress" = "0xfff80000"
136 chip southbridge/via/vt8231
137 register "enable_native_ide" = "0"
138 register "enable_com_ports" = "1"
139 register "enable_keyboard" = "0"
140 device pci 11.0 on # Southbrdge
141 chip superio/winbond/w83627hf
142 device pnp 2e.0 on # Floppy
147 device pnp 2e.1 off # Parallel Port
151 device pnp 2e.2 on # Com1
155 device pnp 2e.3 off # Com2
159 device pnp 2e.5 on # Keyboard
165 register "com1" = "{1}"
167 device pnp 2e.6 off end # CIR
168 device pnp 2e.7 off end # GAME_MIDI_GIPO1
169 device pnp 2e.8 off end # GPIO2
170 device pnp 2e.9 off end # GPIO3
171 device pnp 2e.a off end # ACPI
172 device pnp 2e.b on # HW Monitor
176 device pci 11.1 on end # Ide
177 device pci 11.2 off end # Usb port 0-1
178 device pci 11.3 off end # Usb port 2-3
179 device pci 11.4 off end # ACPI
180 device pci 11.5 off end # AC97 Audio
181 device pci 11.6 on end # AC97 Modem
182 device pci 12.0 on end # Ethernet
186 chip cpu/via/model_centaur