src/mainboard/tyan/s4882/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <pc80/mc146818rtc.h>
   8 #include <console/console.h>
   9 #include <lib.h>
  10 #include <cpu/amd/model_fxx_rev.h>
  11 #include "northbridge/amd/amdk8/incoherent_ht.c"
  12 #include "southbridge/amd/amd8111/early_smbus.c"
  13 #include "northbridge/amd/amdk8/raminit.h"
  14 #include "cpu/amd/model_fxx/apic_timer.c"
  15 #include "lib/delay.c"
  16 #include "northbridge/amd/amdk8/reset_test.c"
  17 #include "northbridge/amd/amdk8/debug.c"
  18 #include "superio/winbond/w83627hf/early_serial.c"
  19 #include "cpu/x86/mtrr/earlymtrr.c"
  20 #include "cpu/x86/bist.h"
  21 #include "northbridge/amd/amdk8/setup_resource_map.c"
  22 #include "southbridge/amd/amd8111/early_ctrl.c"
  23
  24 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  25
  26 static void memreset_setup(void)
  27 {
  28    if (is_cpu_pre_c0())
  29         outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  30    else
  31         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  32    outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  33 }
  34
  35 static void memreset(int controllers, const struct mem_controller *ctrl)
  36 {
  37    if (is_cpu_pre_c0()) {
  38         udelay(800);
  39         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  40         udelay(90);
  41    }
  42 }
  43
  44 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  45 {
  46 #define SMBUS_HUB 0x18
  47         int ret,i;
  48         unsigned device=(ctrl->channel0[0])>>8;
  49         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  50         i=2;
  51         do {
  52                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  53         } while ((ret!=0) && (i-->0));
  54
  55         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  56 }
  57
  58 #if 0
  59 static inline void change_i2c_mux(unsigned device)
  60 {
  61 #define SMBUS_HUB 0x18
  62         int ret, i;
  63         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  64         i=2;
  65         do {
  66                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  67                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  68         } while ((ret!=0) && (i-->0));
  69         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  70         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  71 }
  72 #endif
  73
  74 static inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #include "northbridge/amd/amdk8/raminit.c"
  80 #include "northbridge/amd/amdk8/coherent_ht.c"
  81 #include "lib/generic_sdram.c"
  82 #include "resourcemap.c"
  83 #include "cpu/amd/dualcore/dualcore.c"
  84 #include <spd.h>
  85 #include "cpu/amd/car/post_cache_as_ram.c"
  86 #include "cpu/amd/model_fxx/init_cpus.c"
  87
  88 #define RC0 ((1<<2)<<8)
  89 #define RC1 ((1<<1)<<8)
  90 #define RC2 ((1<<4)<<8)
  91 #define RC3 ((1<<3)<<8)
  92
  93 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  94 {
  95         static const uint16_t spd_addr [] = {
  96                         RC0|DIMM0, RC0|DIMM2, 0, 0,
  97                         RC0|DIMM1, RC0|DIMM3, 0, 0,
  98 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  99                         RC1|DIMM0, RC1|DIMM2, 0, 0,
 100                         RC1|DIMM1, RC1|DIMM3, 0, 0,
 101 #endif
 102 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 103                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 104                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 105                         RC3|DIMM0, RC3|DIMM2, 0, 0,
 106                         RC3|DIMM1, RC3|DIMM3, 0, 0,
 107 #endif
 108         };
 109
 110         int needs_reset;
 111         unsigned bsp_apicid = 0, nodes;
 112         struct mem_controller ctrl[8];
 113
 114         if (bist == 0)
 115                 bsp_apicid = init_cpus(cpu_init_detectedx);
 116
 117         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 118         console_init();
 119
 120         /* Halt if there was a built in self test failure */
 121         report_bist_failure(bist);
 122
 123         setup_s4882_resource_map();
 124
 125         needs_reset = setup_coherent_ht_domain();
 126
 127         wait_all_core0_started();
 128 #if CONFIG_LOGICAL_CPUS==1
 129         // It is said that we should start core1 after all core0 launched
 130         start_other_cores();
 131         wait_all_other_cores_started(bsp_apicid);
 132 #endif
 133
 134         // automatically set that for you, but you might meet tight space
 135         needs_reset |= ht_setup_chains_x();
 136
 137         if (needs_reset) {
 138                 print_info("ht reset -\n");
 139                 soft_reset();
 140         }
 141
 142         allow_all_aps_stop(bsp_apicid);
 143
 144         nodes = get_nodes();
 145         //It's the time to set ctrl now;
 146         fill_mem_ctrl(nodes, ctrl, spd_addr);
 147
 148         enable_smbus();
 149
 150         memreset_setup();
 151         sdram_initialize(nodes, ctrl);
 152
 153         post_cache_as_ram();
 154 }