5 #include <device/pci_def.h>
7 #include <device/pnp_def.h>
8 #include <arch/romcc_io.h>
9 #include <cpu/x86/lapic.h>
10 #include "option_table.h"
11 #include "pc80/mc146818rtc_early.c"
12 #include "pc80/serial.c"
13 #include "arch/i386/lib/console.c"
14 #include "ram/ramtest.c"
16 #include <cpu/amd/model_fxx_rev.h>
17 #include "northbridge/amd/amdk8/incoherent_ht.c"
18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
19 #include "northbridge/amd/amdk8/raminit.h"
20 #include "cpu/amd/model_fxx/apic_timer.c"
21 #include "lib/delay.c"
23 #if CONFIG_USE_INIT == 0
24 #include "lib/memcpy.c"
27 #include "cpu/x86/lapic/boot_cpu.c"
28 #include "northbridge/amd/amdk8/reset_test.c"
29 #include "northbridge/amd/amdk8/debug.c"
30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
32 #include "cpu/amd/mtrr/amd_earlymtrr.c"
33 #include "cpu/x86/bist.h"
35 #include "northbridge/amd/amdk8/setup_resource_map.c"
37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
39 static void hard_reset(void)
44 dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3);
49 pci_write_config8(dev, 0x41, 0xf1);
54 static void soft_reset(void)
59 dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0);
62 pci_write_config8(dev, 0x47, 1);
65 static void memreset_setup(void)
67 if (is_cpu_pre_c0()) {
68 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
71 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
73 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
76 static void memreset(int controllers, const struct mem_controller *ctrl)
78 if (is_cpu_pre_c0()) {
80 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
84 static inline void activate_spd_rom(const struct mem_controller *ctrl)
86 #define SMBUS_HUB 0x18
88 unsigned device=(ctrl->channel0[0])>>8;
89 /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
92 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
93 } while ((ret!=0) && (i-->0));
95 smbus_write_byte(SMBUS_HUB, 0x03, 0);
98 static inline void change_i2c_mux(unsigned device)
100 #define SMBUS_HUB 0x18
102 print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
105 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
106 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
107 } while ((ret!=0) && (i-->0));
108 ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
109 print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
113 static inline int spd_read_byte(unsigned device, unsigned address)
115 return smbus_read_byte(device, address);
118 #define K8_4RANK_DIMM_SUPPORT 1
120 #include "northbridge/amd/amdk8/raminit.c"
121 #include "northbridge/amd/amdk8/coherent_ht.c"
122 #include "sdram/generic_sdram.c"
124 /* tyan does not want the default */
125 #include "resourcemap.c"
127 #if CONFIG_LOGICAL_CPUS==1
128 #define SET_NB_CFG_54 1
130 #include "cpu/amd/dualcore/dualcore.c"
132 #define RC0 ((1<<2)<<8)
133 #define RC1 ((1<<1)<<8)
134 #define RC2 ((1<<4)<<8)
135 #define RC3 ((1<<3)<<8)
142 #include "cpu/amd/car/copy_and_run.c"
144 #include "cpu/amd/car/post_cache_as_ram.c"
146 #include "cpu/amd/model_fxx/init_cpus.c"
148 #if USE_FALLBACK_IMAGE == 1
150 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
151 #include "northbridge/amd/amdk8/early_ht.c"
153 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
155 unsigned last_boot_normal_x = last_boot_normal();
157 /* Is this a cpu only reset? or Is this a secondary cpu? */
158 if ((cpu_init_detectedx) || (!boot_cpu())) {
159 if (last_boot_normal_x) {
166 /* Nothing special needs to be done to find bus 0 */
167 /* Allow the HT devices to be found */
169 enumerate_ht_chain();
171 amd8111_enable_rom();
173 /* Is this a deliberate reset by the bios */
174 if (bios_reset_detected() && last_boot_normal_x) {
177 /* This is the primary cpu how should I boot? */
178 else if (do_normal_boot()) {
185 __asm__ volatile ("jmp __normal_image"
187 : "a" (bist), "b" ( cpu_init_detectedx ) /* inputs */
195 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
197 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
200 #if USE_FALLBACK_IMAGE == 1
201 failover_process(bist, cpu_init_detectedx);
203 real_main(bist, cpu_init_detectedx);
207 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
209 static const uint16_t spd_addr [] = {
210 RC0|DIMM0, RC0|DIMM2, 0, 0,
211 RC0|DIMM1, RC0|DIMM3, 0, 0,
212 #if CONFIG_MAX_PHYSICAL_CPUS > 1
213 RC1|DIMM0, RC1|DIMM2, 0, 0,
214 RC1|DIMM1, RC1|DIMM3, 0, 0,
216 #if CONFIG_MAX_PHYSICAL_CPUS > 2
217 RC2|DIMM0, RC2|DIMM2, 0, 0,
218 RC2|DIMM1, RC2|DIMM3, 0, 0,
219 RC3|DIMM0, RC3|DIMM2, 0, 0,
220 RC3|DIMM1, RC3|DIMM3, 0, 0,
225 unsigned cpu_reset = 0;
226 unsigned bsp_apicid = 0;
228 struct mem_controller ctrl[8];
232 bsp_apicid = init_cpus(cpu_init_detectedx);
236 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
240 /* Halt if there was a built in self test failure */
241 report_bist_failure(bist);
243 setup_s4882_resource_map();
245 needs_reset = setup_coherent_ht_domain();
247 #if CONFIG_LOGICAL_CPUS==1
248 // It is said that we should start core1 after all core0 launched
249 wait_all_core0_started();
253 wait_all_aps_started(bsp_apicid);
255 // automatically set that for you, but you might meet tight space
256 needs_reset |= ht_setup_chains_x();
259 print_info("ht reset -\r\n");
263 allow_all_aps_stop(bsp_apicid);
266 //It's the time to set ctrl now;
267 fill_mem_ctrl(nodes, ctrl, spd_addr);
272 sdram_initialize(nodes, ctrl);
274 post_cache_as_ram(cpu_reset);