src/mainboard/tyan/s4882/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <arch/smp/lapic.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "arch/i386/lib/console.c"
  12 #include "ram/ramtest.c"
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/k8/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/p6/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "northbridge/amd/amdk8/cpu_rev.c"
  22 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  23
  24 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  25
  26 static void hard_reset(void)
  27 {
  28         set_bios_reset();
  29
  30         /* enable cf9 */
  31         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  32         /* reset */
  33         outb(0x0e, 0x0cf9);
  34 }
  35
  36 static void soft_reset(void)
  37 {
  38         set_bios_reset();
  39         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  40 }
  41
  42
  43 static void memreset_setup(void)
  44 {
  45    if (is_cpu_pre_c0()) {
  46         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  47    }
  48    else {
  49         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  50    }
  51         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  52 }
  53
  54 static void memreset(int controllers, const struct mem_controller *ctrl)
  55 {
  56    if (is_cpu_pre_c0()) {
  57         udelay(800);
  58         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  59         udelay(90);
  60    }
  61 }
  62
  63 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  64 {
  65         /* Routing Table Node i
  66          *
  67          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  68          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  69          *
  70          * [ 0: 3] Request Route
  71          *     [0] Route to this node
  72          *     [1] Route to Link 0
  73          *     [2] Route to Link 1
  74          *     [3] Route to Link 2
  75          * [11: 8] Response Route
  76          *     [0] Route to this node
  77          *     [1] Route to Link 0
  78          *     [2] Route to Link 1
  79          *     [3] Route to Link 2
  80          * [19:16] Broadcast route
  81          *     [0] Route to this node
  82          *     [1] Route to Link 0
  83          *     [2] Route to Link 1
  84          *     [3] Route to Link 2
  85          */
  86         uint32_t ret=0x00010101; /* default row entry */
  87
  88
  89         static const unsigned int rows_4p[4][4] = {
  90                 { 0x000b0101, 0x00010202, 0x00030808, 0x00010208 },
  91                 { 0x00010202, 0x00070101, 0x00010204, 0x00030404 },
  92                 { 0x00030404, 0x00010204, 0x00070101, 0x00010202 },
  93                 { 0x00010208, 0x00030808, 0x00010202, 0x000b0101 }
  94         };
  95
  96         if (!(node>=maxnodes || row>=maxnodes)) {
  97                 ret=rows_4p[node][row];
  98         }
  99
 100         return ret;
 101 }
 102
 103 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 104 {
 105 #define SMBUS_HUB 0x18
 106         unsigned device=(ctrl->channel0[0])>>8;
 107         smbus_write_byte(SMBUS_HUB , 0x01, device);
 108         smbus_write_byte(SMBUS_HUB , 0x03, 0);
 109 }
 110 #if 0
 111 static inline void change_i2c_mux(unsigned device)
 112 {
 113 #define SMBUS_HUB 0x18
 114         smbus_write_byte(SMBUS_HUB , 0x01, device);
 115         smbus_write_byte(SMBUS_HUB , 0x03, 0);
 116 }
 117 #endif
 118
 119 static inline int spd_read_byte(unsigned device, unsigned address)
 120 {
 121         return smbus_read_byte(device, address);
 122 }
 123
 124 #include "northbridge/amd/amdk8/raminit.c"
 125
 126 #include "northbridge/amd/amdk8/coherent_ht.c"
 127 #include "sdram/generic_sdram.c"
 128
 129 #include "resourcemap.c" /* tyan does not want the default */
 130
 131 #define FIRST_CPU  1
 132 #define SECOND_CPU 1
 133
 134 #define THIRD_CPU  1
 135 #define FOURTH_CPU 1
 136
 137 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
 138
 139 #define RC0 ((1<<1)<<8)
 140 #define RC1 ((1<<2)<<8)
 141 #define RC2 ((1<<3)<<8)
 142 #define RC3 ((1<<4)<<8)
 143
 144 #define DIMM0 0x50
 145 #define DIMM1 0x51
 146 #define DIMM2 0x52
 147 #define DIMM3 0x53
 148
 149 static void main(void)
 150 {
 151         static const struct mem_controller cpu[] = {
 152 #if FIRST_CPU
 153                 {
 154                         .node_id = 0,
 155                         .f0 = PCI_DEV(0, 0x18, 0),
 156                         .f1 = PCI_DEV(0, 0x18, 1),
 157                         .f2 = PCI_DEV(0, 0x18, 2),
 158                         .f3 = PCI_DEV(0, 0x18, 3),
 159                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 160                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 161                 },
 162 #endif
 163 #if SECOND_CPU
 164                 {
 165                         .node_id = 1,
 166                         .f0 = PCI_DEV(0, 0x19, 0),
 167                         .f1 = PCI_DEV(0, 0x19, 1),
 168                         .f2 = PCI_DEV(0, 0x19, 2),
 169                         .f3 = PCI_DEV(0, 0x19, 3),
 170                         .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
 171                         .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
 172
 173                 },
 174 #endif
 175
 176 #if THIRD_CPU
 177                 {
 178                         .node_id = 2,
 179                         .f0 = PCI_DEV(0, 0x1a, 0),
 180                         .f1 = PCI_DEV(0, 0x1a, 1),
 181                         .f2 = PCI_DEV(0, 0x1a, 2),
 182                         .f3 = PCI_DEV(0, 0x1a, 3),
 183                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 184                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 185
 186                 },
 187 #endif
 188 #if FOURTH_CPU
 189                 {
 190                         .node_id = 3,
 191                         .f0 = PCI_DEV(0, 0x1b, 0),
 192                         .f1 = PCI_DEV(0, 0x1b, 1),
 193                         .f2 = PCI_DEV(0, 0x1b, 2),
 194                         .f3 = PCI_DEV(0, 0x1b, 3),
 195                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 196                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 197
 198                 },
 199 #endif
 200         };
 201         int i;
 202         int needs_reset;
 203         enable_lapic();
 204         init_timer();
 205         if (cpu_init_detected()) {
 206                 asm("jmp __cpu_reset");
 207         }
 208         distinguish_cpu_resets();
 209         if (!boot_cpu()) {
 210                 stop_this_cpu();
 211         }
 212         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 213         uart_init();
 214         console_init();
 215         setup_s4882_resource_map();
 216         needs_reset = setup_coherent_ht_domain();
 217         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xa0);
 218         if (needs_reset) {
 219                 print_info("ht reset -\r\n");
 220                 soft_reset();
 221         }
 222
 223 #if 0
 224         dump_pci_devices();
 225 #endif
 226         enable_smbus();
 227 #if 0
 228
 229 //      activate_spd_rom(&cpu[0]);
 230 //      dump_spd_registers(&cpu[0]);
 231
 232 //      for(i=0;i<4;i++) {
 233 //              activate_spd_rom(&cpu[i]);
 234 //              dump_smbus_registers();
 235 //      }
 236         for(i=1;i<256;i=i*2) {
 237                 change_i2c_mux(i);
 238                 dump_smbus_registers();
 239         }
 240
 241 #endif
 242         memreset_setup();
 243         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 244
 245 #if 0
 246         dump_pci_devices();
 247 #endif
 248 #if 0
 249         dump_pci_device(PCI_DEV(0, 0x18, 1));
 250 #endif
 251
 252         /* Check all of memory */
 253 #if 0
 254         msr_t msr;
 255         msr = rdmsr(TOP_MEM2);
 256         print_debug("TOP_MEM2: ");
 257         print_debug_hex32(msr.hi);
 258         print_debug_hex32(msr.lo);
 259         print_debug("\r\n");
 260 #endif
 261 /*
 262 #if  0
 263         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 264 #else
 265 #if TOTAL_CPUS < 2
 266         // Check 16MB of memory @ 0
 267         ram_check(0x00000000, 0x01000000);
 268 #else
 269         // Check 16MB of memory @ 2GB
 270         ram_check(0x80000000, 0x81000000);
 271 #endif
 272 #endif
 273 */
 274 }