src/mainboard/tyan/s4882/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "northbridge/amd/amdk8/cpu_rev.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 static void hard_reset(void)
  31 {
  32         set_bios_reset();
  33
  34         /* enable cf9 */
  35         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  36         /* reset */
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void soft_reset(void)
  41 {
  42         set_bios_reset();
  43         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  44 }
  45
  46 static void soft2_reset(void)
  47 {
  48         set_bios_reset();
  49         pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
  50 }
  51
  52 static void memreset_setup(void)
  53 {
  54    if (is_cpu_pre_c0()) {
  55         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  56    }
  57    else {
  58         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  59    }
  60         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  61 }
  62
  63 static void memreset(int controllers, const struct mem_controller *ctrl)
  64 {
  65    if (is_cpu_pre_c0()) {
  66         udelay(800);
  67         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  68         udelay(90);
  69    }
  70 }
  71
  72 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  73 {
  74         /* Routing Table Node i
  75          *
  76          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  77          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  78          *
  79          * [ 0: 3] Request Route
  80          *     [0] Route to this node
  81          *     [1] Route to Link 0
  82          *     [2] Route to Link 1
  83          *     [3] Route to Link 2
  84          * [11: 8] Response Route
  85          *     [0] Route to this node
  86          *     [1] Route to Link 0
  87          *     [2] Route to Link 1
  88          *     [3] Route to Link 2
  89          * [19:16] Broadcast route
  90          *     [0] Route to this node
  91          *     [1] Route to Link 0
  92          *     [2] Route to Link 1
  93          *     [3] Route to Link 2
  94          */
  95         uint32_t ret=0x00010101; /* default row entry */
  96
  97 /*
  98             (L2)       (L1)
  99         CPU3-------------CPU1
 100      (L0)|                |(L0)
 101          |                |
 102          |                |
 103          |                |
 104          |                |
 105      (L0)|                |(L0)
 106         CPU2-------------CPU0---------8131----------8111
 107             (L1)       (L2)  (L1)
 108 */
 109
 110         /* Link0 of CPU0 to Link0 of CPU1 */
 111         /* Link2 of CPU0 to Link1 of CPU2 */
 112         /* Link1 of CPU1 to Link2 of CPU3 */
 113         /* Link0 of CPU2 to Link0 of CPU3 */
 114
 115         static const unsigned int rows_4p[4][4] = {
 116                 { 0x000b0101, 0x00010202, 0x00030808, 0x00010208 },
 117                 { 0x00010202, 0x00070101, 0x00010204, 0x00030404 },
 118                 { 0x00030404, 0x00010204, 0x00070101, 0x00010202 },
 119                 { 0x00010208, 0x00030808, 0x00010202, 0x000b0101 }
 120         };
 121
 122         if (!(node>=maxnodes || row>=maxnodes)) {
 123                 ret=rows_4p[node][row];
 124         }
 125
 126         return ret;
 127 }
 128
 129 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 130 {
 131 #define SMBUS_HUB 0x18
 132         unsigned device=(ctrl->channel0[0])>>8;
 133         smbus_write_byte(SMBUS_HUB , 0x01, device);
 134         smbus_write_byte(SMBUS_HUB , 0x03, 0);
 135 }
 136 #if 0
 137 static inline void change_i2c_mux(unsigned device)
 138 {
 139 #define SMBUS_HUB 0x18
 140         smbus_write_byte(SMBUS_HUB , 0x01, device);
 141         smbus_write_byte(SMBUS_HUB , 0x03, 0);
 142 }
 143 #endif
 144
 145 static inline int spd_read_byte(unsigned device, unsigned address)
 146 {
 147         return smbus_read_byte(device, address);
 148 }
 149
 150 //#include "northbridge/amd/amdk8/setup_resource_map.c"
 151 #include "northbridge/amd/amdk8/raminit.c"
 152
 153 #include "northbridge/amd/amdk8/coherent_ht.c"
 154 #include "sdram/generic_sdram.c"
 155
 156  /* tyan does not want the default */
 157 #include "resourcemap.c"
 158
 159 #define FIRST_CPU  1
 160 #define SECOND_CPU 1
 161
 162 #define THIRD_CPU  1
 163 #define FOURTH_CPU 1
 164
 165 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
 166
 167 #define RC0 ((1<<1)<<8)
 168 #define RC1 ((1<<2)<<8)
 169 #define RC2 ((1<<3)<<8)
 170 #define RC3 ((1<<4)<<8)
 171
 172 #define DIMM0 0x50
 173 #define DIMM1 0x51
 174 #define DIMM2 0x52
 175 #define DIMM3 0x53
 176
 177 static void main(unsigned long bist)
 178 {
 179         static const struct mem_controller cpu[] = {
 180 #if FIRST_CPU
 181                 {
 182                         .node_id = 0,
 183                         .f0 = PCI_DEV(0, 0x18, 0),
 184                         .f1 = PCI_DEV(0, 0x18, 1),
 185                         .f2 = PCI_DEV(0, 0x18, 2),
 186                         .f3 = PCI_DEV(0, 0x18, 3),
 187                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 188                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 189                 },
 190 #endif
 191 #if SECOND_CPU
 192                 {
 193                         .node_id = 1,
 194                         .f0 = PCI_DEV(0, 0x19, 0),
 195                         .f1 = PCI_DEV(0, 0x19, 1),
 196                         .f2 = PCI_DEV(0, 0x19, 2),
 197                         .f3 = PCI_DEV(0, 0x19, 3),
 198                         .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
 199                         .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
 200
 201                 },
 202 #endif
 203
 204 #if THIRD_CPU
 205                 {
 206                         .node_id = 2,
 207                         .f0 = PCI_DEV(0, 0x1a, 0),
 208                         .f1 = PCI_DEV(0, 0x1a, 1),
 209                         .f2 = PCI_DEV(0, 0x1a, 2),
 210                         .f3 = PCI_DEV(0, 0x1a, 3),
 211                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 212                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 213
 214                 },
 215 #endif
 216 #if FOURTH_CPU
 217                 {
 218                         .node_id = 3,
 219                         .f0 = PCI_DEV(0, 0x1b, 0),
 220                         .f1 = PCI_DEV(0, 0x1b, 1),
 221                         .f2 = PCI_DEV(0, 0x1b, 2),
 222                         .f3 = PCI_DEV(0, 0x1b, 3),
 223                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 224                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 225
 226                 },
 227 #endif
 228         };
 229         int i;
 230         int needs_reset;
 231         if (bist == 0) {
 232                 /* Skip this if there was a built in self test failure */
 233                 amd_early_mtrr_init();
 234                 enable_lapic();
 235                 init_timer();
 236
 237                 if (cpu_init_detected()) {
 238 #if 1
 239                         asm volatile ("jmp __cpu_reset");
 240 #else
 241                 /* cpu reset also reset the memtroller ????
 242                         need soft_reset to reset all except keep HT link freq and width */
 243                         distinguish_cpu_resets();
 244                         soft2_reset();
 245 #endif
 246                 }
 247                 distinguish_cpu_resets();
 248                 if (!boot_cpu()) {
 249                         stop_this_cpu();
 250                 }
 251         }
 252
 253         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 254         uart_init();
 255         console_init();
 256
 257         /* Halt if there was a built in self test failure */
 258         report_bist_failure(bist);
 259
 260         setup_s4882_resource_map();
 261         needs_reset = setup_coherent_ht_domain();
 262         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xa0);
 263         if (needs_reset) {
 264                 print_info("ht reset -\r\n");
 265                 soft_reset();
 266         }
 267
 268 #if 0
 269         dump_pci_devices();
 270 #endif
 271         enable_smbus();
 272 #if 0
 273
 274 //      activate_spd_rom(&cpu[0]);
 275 //      dump_spd_registers(&cpu[0]);
 276
 277 //      for(i=0;i<4;i++) {
 278 //              activate_spd_rom(&cpu[i]);
 279 //              dump_smbus_registers();
 280 //      }
 281         for(i=1;i<256;i=i*2) {
 282                 change_i2c_mux(i);
 283                 dump_smbus_registers();
 284         }
 285
 286 #endif
 287         memreset_setup();
 288         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 289
 290 #if 0
 291         dump_pci_devices();
 292 #endif
 293 #if 0
 294         dump_pci_device(PCI_DEV(0, 0x18, 1));
 295 #endif
 296
 297         /* Check all of memory */
 298 #if 0
 299         msr_t msr;
 300         msr = rdmsr(TOP_MEM2);
 301         print_debug("TOP_MEM2: ");
 302         print_debug_hex32(msr.hi);
 303         print_debug_hex32(msr.lo);
 304         print_debug("\r\n");
 305 #endif
 306 /*
 307 #if  0
 308         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 309 #else
 310 #if TOTAL_CPUS < 2
 311         // Check 16MB of memory @ 0
 312         ram_check(0x00000000, 0x01000000);
 313 #else
 314         // Check 16MB of memory @ 2GB
 315         ram_check(0x80000000, 0x81000000);
 316 #endif
 317 #endif
 318 */
 319 }