1 uses CONFIG_GENERATE_MP_TABLE
2 uses CONFIG_GENERATE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
21 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_XIP_ROM_SIZE
24 uses CONFIG_XIP_ROM_BASE
25 uses CONFIG_STACK_SIZE
27 uses CONFIG_USE_OPTION_TABLE
28 uses CONFIG_LB_CKS_RANGE_START
29 uses CONFIG_LB_CKS_RANGE_END
30 uses CONFIG_LB_CKS_LOC
32 uses CONFIG_MAINBOARD_PART_NUMBER
33 uses CONFIG_MAINBOARD_VENDOR
34 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
35 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
36 uses COREBOOT_EXTRA_VERSION
38 uses CONFIG_TTYS0_BAUD
39 uses CONFIG_TTYS0_BASE
41 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
42 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
43 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
44 uses CONFIG_CONSOLE_SERIAL8250
45 uses CONFIG_HAVE_INIT_TIMER
48 uses CONFIG_CROSS_COMPILE
52 uses CONFIG_CONSOLE_VGA
53 uses CONFIG_PCI_ROM_RUN
54 uses CONFIG_HW_MEM_HOLE_SIZEK
56 uses CONFIG_USE_DCACHE_RAM
57 uses CONFIG_DCACHE_RAM_BASE
58 uses CONFIG_DCACHE_RAM_SIZE
60 uses CONFIG_USE_PRINTK_IN_CAR
62 uses CONFIG_ENABLE_APIC_EXT_ID
63 uses CONFIG_APIC_ID_OFFSET
64 uses CONFIG_LIFT_BSP_APIC_ID
71 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
73 default CONFIG_ROM_SIZE=524288
76 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
78 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
81 ## Build code for the fallback boot
83 default CONFIG_HAVE_FALLBACK_BOOT=1
86 ## Build code to reset the motherboard from coreboot
88 default CONFIG_HAVE_HARD_RESET=1
91 ## Build code to export a programmable irq routing table
93 default CONFIG_GENERATE_PIRQ_TABLE=1
94 default CONFIG_IRQ_SLOT_COUNT=22
97 ## Build code to export an x86 MP table
98 ## Useful for specifying IRQ routing values
100 default CONFIG_GENERATE_MP_TABLE=1
103 ## Build code to export a CMOS option table
105 default CONFIG_HAVE_OPTION_TABLE=1
108 ## Move the default coreboot cmos range off of AMD RTC registers
110 default CONFIG_LB_CKS_RANGE_START=49
111 default CONFIG_LB_CKS_RANGE_END=122
112 default CONFIG_LB_CKS_LOC=123
115 ## Build code for SMP support
116 ## Only worry about 2 micro processors
119 default CONFIG_MAX_CPUS=8
120 default CONFIG_MAX_PHYSICAL_CPUS=4
121 default CONFIG_LOGICAL_CPUS=1
124 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
127 #default CONFIG_CONSOLE_VGA=1
128 #default CONFIG_PCI_ROM_RUN=1
132 ## enable CACHE_AS_RAM specifics
134 default CONFIG_USE_DCACHE_RAM=1
135 default CONFIG_DCACHE_RAM_BASE=0xcf000
136 default CONFIG_DCACHE_RAM_SIZE=0x1000
137 default CONFIG_USE_INIT=0
139 default CONFIG_ENABLE_APIC_EXT_ID=1
140 default CONFIG_APIC_ID_OFFSET=0x10
141 default CONFIG_LIFT_BSP_APIC_ID=0
144 ## Build code to setup a generic IOAPIC
146 default CONFIG_IOAPIC=1
149 ## Clean up the motherboard id strings
151 default CONFIG_MAINBOARD_VENDOR="Tyan"
152 default CONFIG_MAINBOARD_PART_NUMBER="s4882"
153 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
154 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882
157 ### coreboot layout values
160 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
161 default CONFIG_ROM_IMAGE_SIZE = 65536
164 ## Use a small 8K stack
166 default CONFIG_STACK_SIZE=0x2000
169 ## Use a small 16K heap
171 default CONFIG_HEAP_SIZE=0x4000
174 ## Only use the option table in a normal image
176 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
179 ## Coreboot C code runs at this location in RAM
181 default CONFIG_RAMBASE=0x00002000
184 ## Load the payload from the ROM
186 default CONFIG_ROM_PAYLOAD = 1
189 ### Defaults of options that you may want to override in the target config file
193 ## The default compiler
195 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
199 ## Disable the gdb stub by default
201 default CONFIG_GDB_STUB=0
203 default CONFIG_USE_PRINTK_IN_CAR=1
206 ## The Serial Console
209 # To Enable the Serial Console
210 default CONFIG_CONSOLE_SERIAL8250=1
212 ## Select the serial console baud rate
213 default CONFIG_TTYS0_BAUD=115200
214 #default CONFIG_TTYS0_BAUD=57600
215 #default CONFIG_TTYS0_BAUD=38400
216 #default CONFIG_TTYS0_BAUD=19200
217 #default CONFIG_TTYS0_BAUD=9600
218 #default CONFIG_TTYS0_BAUD=4800
219 #default CONFIG_TTYS0_BAUD=2400
220 #default CONFIG_TTYS0_BAUD=1200
222 # Select the serial console base port
223 default CONFIG_TTYS0_BASE=0x3f8
225 # Select the serial protocol
226 # This defaults to 8 data bits, 1 stop bit, and no parity
227 default CONFIG_TTYS0_LCS=0x3
230 ### Select the coreboot loglevel
232 ## EMERG 1 system is unusable
233 ## ALERT 2 action must be taken immediately
234 ## CRIT 3 critical conditions
235 ## ERR 4 error conditions
236 ## WARNING 5 warning conditions
237 ## NOTICE 6 normal but significant condition
238 ## INFO 7 informational
239 ## CONFIG_DEBUG 8 debug-level messages
240 ## SPEW 9 Way too many details
242 ## Request this level of debugging output
243 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
244 ## At a maximum only compile in this level of debugging
245 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
248 ## Select power on after power fail setting
249 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"