src/mainboard/tyan/s4880/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "console/console.c"
  14 #include "lib/ramtest.c"
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22
  23 #include "cpu/x86/lapic/boot_cpu.c"
  24 #include "northbridge/amd/amdk8/reset_test.c"
  25 #include "northbridge/amd/amdk8/debug.c"
  26 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  27
  28 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  29 #include "cpu/x86/bist.h"
  30
  31 #include "northbridge/amd/amdk8/setup_resource_map.c"
  32
  33 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  34
  35 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  36
  37 static void memreset_setup(void)
  38 {
  39    if (is_cpu_pre_c0()) {
  40         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  41    }
  42    else {
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  44    }
  45         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  46 }
  47
  48 static void memreset(int controllers, const struct mem_controller *ctrl)
  49 {
  50    if (is_cpu_pre_c0()) {
  51         udelay(800);
  52         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  53         udelay(90);
  54    }
  55 }
  56 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  57 {
  58 #define SMBUS_HUB 0x18
  59         unsigned device=(ctrl->channel0[0])>>8;
  60         smbus_write_byte(SMBUS_HUB, 0x01, device);
  61         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  62 }
  63 #if 0
  64 static inline void change_i2c_mux(unsigned device)
  65 {
  66 #define SMBUS_HUB 0x18
  67         int ret;
  68         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  69         ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  70         print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  71         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  72         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  73 }
  74 #endif
  75
  76 static inline int spd_read_byte(unsigned device, unsigned address)
  77 {
  78         return smbus_read_byte(device, address);
  79 }
  80
  81 #define QRANK_DIMM_SUPPORT 1
  82
  83 #include "northbridge/amd/amdk8/raminit.c"
  84 #include "northbridge/amd/amdk8/coherent_ht.c"
  85 #include "lib/generic_sdram.c"
  86
  87  /* tyan does not want the default */
  88 #include "resourcemap.c"
  89
  90 #if CONFIG_LOGICAL_CPUS==1
  91 #define SET_NB_CFG_54 1
  92 #endif
  93 #include "cpu/amd/dualcore/dualcore.c"
  94
  95 #define RC0 ((1<<2)<<8)
  96 #define RC1 ((1<<1)<<8)
  97 #define RC2 ((1<<4)<<8)
  98 #define RC3 ((1<<3)<<8)
  99
 100 #define DIMM0 0x50
 101 #define DIMM1 0x51
 102 #define DIMM2 0x52
 103 #define DIMM3 0x53
 104
 105
 106
 107 #include "cpu/amd/car/post_cache_as_ram.c"
 108
 109 #include "cpu/amd/model_fxx/init_cpus.c"
 110
 111 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 112 #include "northbridge/amd/amdk8/early_ht.c"
 113
 114 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 115 {
 116         static const struct mem_controller cpu[] = {
 117                 {
 118                         .node_id = 0,
 119                         .f0 = PCI_DEV(0, 0x18, 0),
 120                         .f1 = PCI_DEV(0, 0x18, 1),
 121                         .f2 = PCI_DEV(0, 0x18, 2),
 122                         .f3 = PCI_DEV(0, 0x18, 3),
 123                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 124                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 125                 },
 126 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 127                 {
 128                         .node_id = 1,
 129                         .f0 = PCI_DEV(0, 0x19, 0),
 130                         .f1 = PCI_DEV(0, 0x19, 1),
 131                         .f2 = PCI_DEV(0, 0x19, 2),
 132                         .f3 = PCI_DEV(0, 0x19, 3),
 133                         .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
 134                         .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
 135
 136                 },
 137 #endif
 138
 139 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 140                 {
 141                         .node_id = 2,
 142                         .f0 = PCI_DEV(0, 0x1a, 0),
 143                         .f1 = PCI_DEV(0, 0x1a, 1),
 144                         .f2 = PCI_DEV(0, 0x1a, 2),
 145                         .f3 = PCI_DEV(0, 0x1a, 3),
 146                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 147                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 148
 149                 },
 150                 {
 151                         .node_id = 3,
 152                         .f0 = PCI_DEV(0, 0x1b, 0),
 153                         .f1 = PCI_DEV(0, 0x1b, 1),
 154                         .f2 = PCI_DEV(0, 0x1b, 2),
 155                         .f3 = PCI_DEV(0, 0x1b, 3),
 156                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 157                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 158
 159                 },
 160 #endif
 161         };
 162
 163         int needs_reset;
 164
 165         if (!cpu_init_detectedx && boot_cpu()) {
 166                 /* Nothing special needs to be done to find bus 0 */
 167                 /* Allow the HT devices to be found */
 168
 169                 enumerate_ht_chain();
 170
 171                 amd8111_enable_rom();
 172         }
 173
 174         if (bist == 0) {
 175                 init_cpus(cpu_init_detectedx);
 176         }
 177
 178         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 179         uart_init();
 180         console_init();
 181
 182         /* Halt if there was a built in self test failure */
 183         report_bist_failure(bist);
 184
 185         setup_s4880_resource_map();
 186
 187         needs_reset = setup_coherent_ht_domain();
 188
 189 #if CONFIG_LOGICAL_CPUS==1
 190         // It is said that we should start core1 after all core0 launched
 191         start_other_cores();
 192 #endif
 193         // automatically set that for you, but you might meet tight space
 194         needs_reset |= ht_setup_chains_x();
 195
 196         if (needs_reset) {
 197                 print_info("ht reset -\n");
 198                 soft_reset();
 199         }
 200
 201         enable_smbus();
 202
 203         memreset_setup();
 204         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 205
 206         post_cache_as_ram();
 207 }
 208