3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
9 #include <pc80/mc146818rtc.h>
10 #include <console/console.h>
12 #include <cpu/amd/model_fxx_rev.h>
13 #include "northbridge/amd/amdk8/incoherent_ht.c"
14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
15 #include "northbridge/amd/amdk8/raminit.h"
16 #include "cpu/amd/model_fxx/apic_timer.c"
17 #include "lib/delay.c"
18 #include "cpu/x86/lapic/boot_cpu.c"
19 #include "northbridge/amd/amdk8/reset_test.c"
20 #include "northbridge/amd/amdk8/debug.c"
21 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
22 #include "cpu/x86/mtrr/earlymtrr.c"
23 #include "cpu/x86/bist.h"
24 #include "northbridge/amd/amdk8/setup_resource_map.c"
25 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
27 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
29 static void memreset_setup(void)
31 if (is_cpu_pre_c0()) {
32 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
35 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
37 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
40 static void memreset(int controllers, const struct mem_controller *ctrl)
42 if (is_cpu_pre_c0()) {
44 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
48 static inline void activate_spd_rom(const struct mem_controller *ctrl)
50 #define SMBUS_HUB 0x18
51 unsigned device=(ctrl->channel0[0])>>8;
52 smbus_write_byte(SMBUS_HUB, 0x01, device);
53 smbus_write_byte(SMBUS_HUB, 0x03, 0);
56 static inline void change_i2c_mux(unsigned device)
58 #define SMBUS_HUB 0x18
60 print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
61 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
62 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
63 ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
64 print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
68 static inline int spd_read_byte(unsigned device, unsigned address)
70 return smbus_read_byte(device, address);
73 #include "northbridge/amd/amdk8/raminit.c"
74 #include "northbridge/amd/amdk8/coherent_ht.c"
75 #include "lib/generic_sdram.c"
76 #include "resourcemap.c" /* tyan does not want the default */
77 #include "cpu/amd/dualcore/dualcore.c"
79 #include "cpu/amd/car/post_cache_as_ram.c"
80 #include "cpu/amd/model_fxx/init_cpus.c"
81 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
82 #include "northbridge/amd/amdk8/early_ht.c"
84 #define RC0 ((1<<2)<<8)
85 #define RC1 ((1<<1)<<8)
86 #define RC2 ((1<<4)<<8)
87 #define RC3 ((1<<3)<<8)
89 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
91 static const struct mem_controller cpu[] = {
94 .f0 = PCI_DEV(0, 0x18, 0),
95 .f1 = PCI_DEV(0, 0x18, 1),
96 .f2 = PCI_DEV(0, 0x18, 2),
97 .f3 = PCI_DEV(0, 0x18, 3),
98 .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
99 .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
101 #if CONFIG_MAX_PHYSICAL_CPUS > 1
104 .f0 = PCI_DEV(0, 0x19, 0),
105 .f1 = PCI_DEV(0, 0x19, 1),
106 .f2 = PCI_DEV(0, 0x19, 2),
107 .f3 = PCI_DEV(0, 0x19, 3),
108 .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
109 .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
114 #if CONFIG_MAX_PHYSICAL_CPUS > 2
117 .f0 = PCI_DEV(0, 0x1a, 0),
118 .f1 = PCI_DEV(0, 0x1a, 1),
119 .f2 = PCI_DEV(0, 0x1a, 2),
120 .f3 = PCI_DEV(0, 0x1a, 3),
121 .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
122 .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
127 .f0 = PCI_DEV(0, 0x1b, 0),
128 .f1 = PCI_DEV(0, 0x1b, 1),
129 .f2 = PCI_DEV(0, 0x1b, 2),
130 .f3 = PCI_DEV(0, 0x1b, 3),
131 .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
132 .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
140 if (!cpu_init_detectedx && boot_cpu()) {
141 /* Nothing special needs to be done to find bus 0 */
142 /* Allow the HT devices to be found */
144 enumerate_ht_chain();
146 amd8111_enable_rom();
150 init_cpus(cpu_init_detectedx);
153 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
157 /* Halt if there was a built in self test failure */
158 report_bist_failure(bist);
160 setup_s4880_resource_map();
162 needs_reset = setup_coherent_ht_domain();
164 #if CONFIG_LOGICAL_CPUS==1
165 // It is said that we should start core1 after all core0 launched
168 // automatically set that for you, but you might meet tight space
169 needs_reset |= ht_setup_chains_x();
172 print_info("ht reset -\n");
179 sdram_initialize(ARRAY_SIZE(cpu), cpu);