src/mainboard/tyan/s4880/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22
  23 #if CONFIG_USE_INIT == 0
  24 #include "lib/memcpy.c"
  25 #endif
  26
  27 #include "cpu/x86/lapic/boot_cpu.c"
  28 #include "northbridge/amd/amdk8/reset_test.c"
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  31
  32 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  33 #include "cpu/x86/bist.h"
  34
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  38
  39 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  40
  41 static void memreset_setup(void)
  42 {
  43    if (is_cpu_pre_c0()) {
  44         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  45    }
  46    else {
  47         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  48    }
  49         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  50 }
  51
  52 static void memreset(int controllers, const struct mem_controller *ctrl)
  53 {
  54    if (is_cpu_pre_c0()) {
  55         udelay(800);
  56         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  57         udelay(90);
  58    }
  59 }
  60 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  61 {
  62 #define SMBUS_HUB 0x18
  63         int ret;
  64         unsigned device=(ctrl->channel0[0])>>8;
  65         smbus_write_byte(SMBUS_HUB, 0x01, device);
  66         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  67 }
  68 #if 0
  69 static inline void change_i2c_mux(unsigned device)
  70 {
  71 #define SMBUS_HUB 0x18
  72         int ret;
  73         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
  74         ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  75         print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
  76         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  77         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
  78 }
  79 #endif
  80
  81 static inline int spd_read_byte(unsigned device, unsigned address)
  82 {
  83         return smbus_read_byte(device, address);
  84 }
  85
  86 #define K8_4RANK_DIMM_SUPPORT 1
  87
  88 #include "northbridge/amd/amdk8/raminit.c"
  89 #include "northbridge/amd/amdk8/coherent_ht.c"
  90 #include "sdram/generic_sdram.c"
  91
  92  /* tyan does not want the default */
  93 #include "resourcemap.c"
  94
  95 #if CONFIG_LOGICAL_CPUS==1
  96 #define SET_NB_CFG_54 1
  97 #endif
  98 #include "cpu/amd/dualcore/dualcore.c"
  99
 100 #define RC0 ((1<<2)<<8)
 101 #define RC1 ((1<<1)<<8)
 102 #define RC2 ((1<<4)<<8)
 103 #define RC3 ((1<<3)<<8)
 104
 105 #define DIMM0 0x50
 106 #define DIMM1 0x51
 107 #define DIMM2 0x52
 108 #define DIMM3 0x53
 109
 110 #include "cpu/amd/car/copy_and_run.c"
 111
 112 #include "cpu/amd/car/post_cache_as_ram.c"
 113
 114 #include "cpu/amd/model_fxx/init_cpus.c"
 115
 116
 117 #if USE_FALLBACK_IMAGE == 1
 118
 119 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 120 #include "northbridge/amd/amdk8/early_ht.c"
 121
 122 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 123 {
 124         unsigned last_boot_normal_x = last_boot_normal();
 125
 126         /* Is this a cpu only reset? or Is this a secondary cpu? */
 127         if ((cpu_init_detectedx) || (!boot_cpu())) {
 128                 if (last_boot_normal_x) {
 129                         goto normal_image;
 130                 } else {
 131                         goto fallback_image;
 132                 }
 133         }
 134
 135         /* Nothing special needs to be done to find bus 0 */
 136         /* Allow the HT devices to be found */
 137
 138         enumerate_ht_chain();
 139
 140         amd8111_enable_rom();
 141
 142         /* Is this a deliberate reset by the bios */
 143         if (bios_reset_detected() && last_boot_normal_x) {
 144                 goto normal_image;
 145         }
 146         /* This is the primary cpu how should I boot? */
 147         else if (do_normal_boot()) {
 148                 goto normal_image;
 149         }
 150         else {
 151                 goto fallback_image;
 152         }
 153  normal_image:
 154         __asm__ volatile ("jmp __normal_image"
 155                 : /* outputs */
 156                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 157                 );
 158
 159  fallback_image:
 160         ;
 161 }
 162 #endif
 163
 164 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 165
 166 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 167 {
 168
 169 #if USE_FALLBACK_IMAGE == 1
 170         failover_process(bist, cpu_init_detectedx);
 171 #endif
 172         real_main(bist, cpu_init_detectedx);
 173
 174 }
 175
 176 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 177 {
 178         static const struct mem_controller cpu[] = {
 179                 {
 180                         .node_id = 0,
 181                         .f0 = PCI_DEV(0, 0x18, 0),
 182                         .f1 = PCI_DEV(0, 0x18, 1),
 183                         .f2 = PCI_DEV(0, 0x18, 2),
 184                         .f3 = PCI_DEV(0, 0x18, 3),
 185                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 186                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 187                 },
 188 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 189                 {
 190                         .node_id = 1,
 191                         .f0 = PCI_DEV(0, 0x19, 0),
 192                         .f1 = PCI_DEV(0, 0x19, 1),
 193                         .f2 = PCI_DEV(0, 0x19, 2),
 194                         .f3 = PCI_DEV(0, 0x19, 3),
 195                         .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
 196                         .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
 197
 198                 },
 199 #endif
 200
 201 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 202                 {
 203                         .node_id = 2,
 204                         .f0 = PCI_DEV(0, 0x1a, 0),
 205                         .f1 = PCI_DEV(0, 0x1a, 1),
 206                         .f2 = PCI_DEV(0, 0x1a, 2),
 207                         .f3 = PCI_DEV(0, 0x1a, 3),
 208                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 209                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 210
 211                 },
 212                 {
 213                         .node_id = 3,
 214                         .f0 = PCI_DEV(0, 0x1b, 0),
 215                         .f1 = PCI_DEV(0, 0x1b, 1),
 216                         .f2 = PCI_DEV(0, 0x1b, 2),
 217                         .f3 = PCI_DEV(0, 0x1b, 3),
 218                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 219                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 220
 221                 },
 222 #endif
 223         };
 224
 225         int needs_reset;
 226
 227         if (bist == 0) {
 228                 init_cpus(cpu_init_detectedx);
 229         }
 230
 231         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 232         uart_init();
 233         console_init();
 234
 235         /* Halt if there was a built in self test failure */
 236         report_bist_failure(bist);
 237
 238         setup_s4880_resource_map();
 239
 240         needs_reset = setup_coherent_ht_domain();
 241
 242 #if CONFIG_LOGICAL_CPUS==1
 243         // It is said that we should start core1 after all core0 launched
 244         start_other_cores();
 245 #endif
 246         // automatically set that for you, but you might meet tight space
 247         needs_reset |= ht_setup_chains_x();
 248
 249         if (needs_reset) {
 250                 print_info("ht reset -\r\n");
 251                 soft_reset();
 252         }
 253
 254         enable_smbus();
 255
 256         memreset_setup();
 257         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 258
 259         post_cache_as_ram();
 260 }