src/mainboard/tyan/s4880/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "northbridge/amd/amdk8/cpu_rev.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 static void hard_reset(void)
  31 {
  32         set_bios_reset();
  33
  34         /* enable cf9 */
  35         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  36         /* reset */
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void soft_reset(void)
  41 {
  42         set_bios_reset();
  43         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  44 }
  45
  46 static void memreset_setup(void)
  47 {
  48    if (is_cpu_pre_c0()) {
  49         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  50    }
  51    else {
  52         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  53    }
  54         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  55 }
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl)
  58 {
  59    if (is_cpu_pre_c0()) {
  60         udelay(800);
  61         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  62         udelay(90);
  63    }
  64 }
  65
  66 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  67 {
  68 #define SMBUS_HUB 0x18
  69         unsigned device=(ctrl->channel0[0])>>8;
  70         smbus_write_byte(SMBUS_HUB , 0x01, device);
  71         smbus_write_byte(SMBUS_HUB , 0x03, 0);
  72 }
  73
  74 static inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #include "northbridge/amd/amdk8/setup_resource_map.c"
  80 #include "northbridge/amd/amdk8/raminit.c"
  81
  82 #include "northbridge/amd/amdk8/coherent_ht.c"
  83 #include "sdram/generic_sdram.c"
  84
  85  /* tyan does not want the default */
  86 #include "resourcemap.c"
  87
  88 #if CONFIG_LOGICAL_CPUS==1
  89 #define SET_NB_CFG_54 1
  90 #include "cpu/amd/dualcore/dualcore.c"
  91 #endif
  92
  93 #define FIRST_CPU  1
  94 #define SECOND_CPU 1
  95
  96 #define THIRD_CPU  1
  97 #define FOURTH_CPU 1
  98
  99 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
 100
 101 #define RC0 ((1<<1)<<8)
 102 #define RC1 ((1<<2)<<8)
 103 #define RC2 ((1<<3)<<8)
 104 #define RC3 ((1<<4)<<8)
 105
 106 #define DIMM0 0x50
 107 #define DIMM1 0x51
 108 #define DIMM2 0x52
 109 #define DIMM3 0x53
 110
 111 static void main(unsigned long bist)
 112 {
 113         static const struct mem_controller cpu[] = {
 114 #if FIRST_CPU
 115                 {
 116                         .node_id = 0,
 117                         .f0 = PCI_DEV(0, 0x18, 0),
 118                         .f1 = PCI_DEV(0, 0x18, 1),
 119                         .f2 = PCI_DEV(0, 0x18, 2),
 120                         .f3 = PCI_DEV(0, 0x18, 3),
 121                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 122                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 123                 },
 124 #endif
 125 #if SECOND_CPU
 126                 {
 127                         .node_id = 1,
 128                         .f0 = PCI_DEV(0, 0x19, 0),
 129                         .f1 = PCI_DEV(0, 0x19, 1),
 130                         .f2 = PCI_DEV(0, 0x19, 2),
 131                         .f3 = PCI_DEV(0, 0x19, 3),
 132                         .channel0 = { RC1|DIMM0, 0 , 0, 0 },
 133                         .channel1 = { RC1|DIMM1, 0, 0, 0 },
 134
 135                 },
 136 #endif
 137
 138 #if THIRD_CPU
 139                 {
 140                         .node_id = 2,
 141                         .f0 = PCI_DEV(0, 0x1a, 0),
 142                         .f1 = PCI_DEV(0, 0x1a, 1),
 143                         .f2 = PCI_DEV(0, 0x1a, 2),
 144                         .f3 = PCI_DEV(0, 0x1a, 3),
 145                         .channel0 = { RC2|DIMM0, 0, 0, 0 },
 146                         .channel1 = { RC2|DIMM1, 0, 0, 0 },
 147
 148                 },
 149 #endif
 150 #if FOURTH_CPU
 151                 {
 152                         .node_id = 3,
 153                         .f0 = PCI_DEV(0, 0x1b, 0),
 154                         .f1 = PCI_DEV(0, 0x1b, 1),
 155                         .f2 = PCI_DEV(0, 0x1b, 2),
 156                         .f3 = PCI_DEV(0, 0x1b, 3),
 157                         .channel0 = { RC3|DIMM0, 0, 0, 0 },
 158                         .channel1 = { RC3|DIMM1, 0, 0, 0 },
 159
 160                 },
 161 #endif
 162         };
 163         int i;
 164         int needs_reset;
 165 #if CONFIG_LOGICAL_CPUS==1
 166         struct node_core_id id;
 167 #else
 168         unsigned nodeid;
 169 #endif
 170
 171         if (bist == 0) {
 172                 /* Skip this if there was a built in self test failure */
 173                 amd_early_mtrr_init();
 174
 175 #if CONFIG_LOGICAL_CPUS==1
 176                 set_apicid_cpuid_lo();
 177 #endif
 178
 179                 enable_lapic();
 180                 init_timer();
 181
 182 #if CONFIG_LOGICAL_CPUS==1
 183                 id = get_node_core_id_x();
 184                 if(id.coreid == 0) {
 185                         if (cpu_init_detected(id.nodeid)) {
 186                                 asm volatile ("jmp __cpu_reset");
 187                         }
 188                         distinguish_cpu_resets(id.nodeid);
 189                 }
 190 #else
 191                 nodeid = lapicid();
 192                 if (cpu_init_detected(nodeid)) {
 193                         asm volatile ("jmp __cpu_reset");
 194                 }
 195                 distinguish_cpu_resets(nodeid);
 196 #endif
 197
 198                 if (!boot_cpu()
 199 #if CONFIG_LOGICAL_CPUS==1
 200                         || (id.coreid != 0)
 201 #endif
 202                 ) {
 203                         stop_this_cpu();
 204                 }
 205         }
 206
 207         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 208         uart_init();
 209         console_init();
 210
 211         /* Halt if there was a built in self test failure */
 212         report_bist_failure(bist);
 213
 214         setup_s4880_resource_map();
 215
 216         needs_reset = setup_coherent_ht_domain();
 217
 218 #if CONFIG_LOGICAL_CPUS==1
 219         start_other_cores();
 220 #endif
 221
 222         // automatically set that for you, but you might meet tight space
 223         needs_reset |= ht_setup_chains_x();
 224
 225         if (needs_reset) {
 226                 print_info("ht reset -\r\n");
 227                 soft_reset();
 228         }
 229
 230         enable_smbus();
 231
 232         memreset_setup();
 233         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 234
 235 }